ADF4193BCPZ Analog Devices Inc, ADF4193BCPZ Datasheet - Page 23

• Manufacturer Part Number: ADF4193BCPZ
• Description: IC PLL FREQ SYNTHESIZER 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4193BCPZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 3.5GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Frequency-max: 3.5GHz
• Pll Type: Frequency Synthesis
• Frequency: 3.5GHz
• Supply Current: 24mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 32
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4193EBZ2 - BOARD EVALUATION EB2 FOR ADF4193EVAL-ADF4193EBZ1 - BOARD EVALUATION EB1 FOR ADF4193
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

The 8:1 loop bandwidth switching ratio of the ADF4193 makes
it possible to attenuate all spurs to sufficiently low levels for
most applications. The final loop BW can be chosen to ensure
that all spurs are far enough out of band while meeting the lock
time requirements with the 8× bandwidth boost.
The ADF4193 programmable modulus and R divider can also
be used to avoid integer boundary channels. This option is
described in the Avoiding Integer Boundary Channels section.
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers as the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. One such mechanism
is feedthrough of low levels of on-chip reference switching noise
out through the RF
spur levels as high as –90 dBc. These spurs can be suppressed
below –110 dBc by inserting sufficient reverse isolation, for
example, through an RF buffer between the VCO and RF
In addition, care should be taken in the PCB layout to ensure
that the VCO is well separated from the input reference to avoid
a possible feedthrough path on the board.
POWER-UP INITIALIZATION
After applying power to the ADF4193, a 14-step sequence is
recommended, as described in Table 8.
The divider and timer setting used in the example in Table 8 is
for a DCS1800 Tx synthesizer with a 104 MHz REF
Table 8. Power-Up Initialization Sequence
Step
1
2
Wait
10 ms
3
4
5
6
7
8
9
10
11
12
13
14
Register
Bits
R5 [7:0]
R3 [15:0]
R7 [15:0]
R6 [15:0]
R6 [15:0]
R4 [23:0]
R4 [23:0]
R4 [23:0]
R2 [15:0]
R1 [23:0]
R0 [23:0]
R3 [15:0]
R5 [7:0]
R0 [23:0]
IN
pin back to the VCO, resulting in reference
Hex
Codes
FD
005B
0007
000E
900E
004464
00446C
004394
00D2
520209
480140
007B
05
480140
Description
Set all power-down bits.
PD polarity = 1, ground CP
CP
Allow time for loop filter
capacitors to discharge.
Clear test modes.
Initialize PLL modes, digital lock
detect on MUX
10 ns lock detect threshold,
digital lock detect on MUX
SW1/SW2 timer = 10.8 μs.
SW3 timer = 10.8 μs.
ICP timer = 8.6 μs.
Phase = 26.
8/9 prescaler, doubler disabled,
R = 4, toggle FF on, MOD = 65.
INT = 144, FRAC = 40 for
1880 MHz output frequency.
PD polarity = 1, release CP
CP
Clear all power-down bits.
INT = 144, FRAC = 40 for
1880 MHz output frequency.
OUT
OUT
–.
–.
OUT
.
IN
frequency.
IN
OUT
OUT+
OUT
pin.
Rev. C | Page 23 of 28
+/
.
/
The ADF4193 powers up after Step 13. It locks to the
programmed channel frequency after Step 14.
CHANGING THE FREQUENCY OF THE PLL AND THE
PHASE LOOK-UP TABLE
Once the ADF4193 is initialized, a write to Register R0 is all
that is required to program a new output frequency. The N
divider is updated with the values of INT and FRAC on the next
PFD cycle following the LE edge that latches in the R0 word.
However, the settling time and spurious performance of the
synthesizer can be further optimized by modifying R1 and R2
register settings on a channel-by-channel basis. These settings
are double buffered by the write to R0. This means that while
the data is loaded in through the serial interface on the
respective R1 and R2 write cycles, the synthesizer is not
updated with their data until the next write to Register R0.
The R2 register can be used to digitally adjust the phase of the
VCO output relative to the reference edge. The phase can be
adjusted over the full 360° range at RF with a resolution of
360°/MOD. In most frequency synthesizer applications, the
actual phase offset of the VCO output with respect to the
reference is unknown and does not matter. In such applications,
the phase adjustment capability of the R2 register can instead be
used to optimize the settling time performance, as described in
the Phase Look-Up Table section.
Phase Look-Up Table
The ADF4193’s fast lock sequence is initiated following the
write to Register R0. The fast lock timers are programmed so
that after the PLL has settled in wide BW mode, the charge
pump current is reduced and loop filter resistor switches are
opened to reduce the loop BW. The reference cycle on which
these events occur is determined by the values preprogrammed
into the timeout counters.
Figure 10 and Figure 13 show that the lock time to final phase
is dominated by the phase swing that occurs when the BW is
reduced. Once the PLL has settled to final frequency and phase,
in wide BW mode, this phase swing is the same, regardless of
the size of the synthesizer’s frequency jump. The amplitude of
the phase swing is related to the current flowing through the
loop filter zero resistors on the PFD reference cycle that the
SW1/SW2 switches are opened. In an integer-N PLL, this
current is zero once the PLL has settled. In a fractional-N PLL,
the current is zero on average but varies from one reference
cycle to the next, depending on the quantization error sequence
output from the digital Σ-Δ modulator. Because the Σ-Δ
modulator is all digital logic, clocked at the PFD reference rate,
for a given value of MOD, the actual quantization error on any
given reference cycle is determined by the value of FRAC and
the PHASE word that the modulator is seeded with, following
the write to R0. By choosing an appropriate value of PHASE,
corresponding to the value of FRAC, that is programmed on the
next write to R0, the size of the error current on the PFD
reference cycle the SW1/SW2 switches opened, and thus the
ADF4193