ADF4193BCPZ Analog Devices Inc, ADF4193BCPZ Datasheet - Page 13

• Manufacturer Part Number: ADF4193BCPZ
• Description: IC PLL FREQ SYNTHESIZER 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4193BCPZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 3.5GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Frequency-max: 3.5GHz
• Pll Type: Frequency Synthesis
• Frequency: 3.5GHz
• Supply Current: 24mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 32
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4193EBZ2 - BOARD EVALUATION EB2 FOR ADF4193EVAL-ADF4193EBZ1 - BOARD EVALUATION EB1 FOR ADF4193
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Differential Amplifier
The internal, low noise, differential-to-single-ended amplifier is
used to convert the differential charge pump output to a single-
ended control voltage for the tuning port of the VCO. Figure 26
shows a simplified schematic of the differential amplifier. The
output voltage is equal to the differential voltage, offset by the
voltage on the CMR pin, according to
The CMR offset voltage is internally biased to three-fifths of
V
Figure 26. Connect a 0.1 μF capacitor to ground to the CMR pin
to roll off the thermal noise of the biasing resistors.
As can be seen in Figure 15, the differential amplifier output
voltage behaves according to the previous equation over a 4 V
range from approximately 1.2 V minimum up to V
However, fast settling is guaranteed only over a tuning voltage
range from 1.8 V up to V
room for overshoot in the PLL frequency settling transient.
Noise from the differential amplifier is suppressed inside the
PLL bandwidth. For loop bandwidths >20 kHz, the 1/f noise has
a negligible effect on the PLL output phase noise. Outside the
loop bandwidth, the differential amplifier’s noise FM modulates
the VCO. The passive filter network following the differential
amplifier, shown in Figure 36, suppresses this noise contribution
to below the VCO noise from offsets of 400 kHz and above.
This network has a negligible effect on lock time because it is
bypassed when SW3 is closed while the loop is locking.
P
F
3, the differential amplifier power supply voltage, as shown in
AIN–
AIN+
PFD
V
WRITE
TO R0
AOUT
= (V
Figure 26. Differential Amplifier Block Diagram
÷4
START
AIN+
Figure 25. Fast Lock Timeout Counters
500Ω
500Ω
CHARGE PUMP
ENABLE LOGIC
− V
COUNTER
TIMEOUT
EN[64:1]
ICP
AIN−
P
500Ω
500Ω
3 − 0.8 V. This is to allow sufficient
) + V
CMR
COUNTER
SW1/SW2
TIMEOUT
V
P
3
20kΩ
30kΩ
COUNTER
TIMEOUT
SW3
AOUT
CMR
P
3 − 0.3 V.
C EXT =
0.1µF
SW3
A
SW1
SW2
SW
OUT
GND
Rev. C | Page 13 of 28
MUX
The output multiplexer on the ADF4193 allows the user to
access various internal points on the chip. The state of MUX
is controlled by M4 to M1 in the MUX register. Figure 35 shows
the full truth table. Figure 27 shows the MUX
block diagram form.
Lock Detect
MUX
signal. Digital lock detect is active high. Its output goes high if
there are 40 successive PFD cycles with an input error of less
than 3 ns. For reliable lock detect operation with RF frequencies
<2 GHz, it is recommended that this threshold be increased to
10 ns by programming Register R6. The digital lock detect goes
low again when a new channel is programmed or when the
error at the PFD input exceeds 30 ns for one or more cycles.
Input Shift Register
The ADF4193 serial interface section includes a 24-bit input
shift register. Data is clocked in MSB first on each rising edge
of CLK. Data from the shift register is latched into one of eight
control registers, R0 to R7, on the rising edge of latch enable
(LE). The destination register is determined by the state of
the three control bits (Control Bit C3, Control Bit C2, and
Control Bit C1) in the shift register. The three LSBs are Bit DB2,
Bit DB1, and Bit DB0, as shown in the timing diagram of Figure 2.
The truth table for these bits is shown in Table 5. Figure 28
shows a summary of how the registers are programmed.
Table 5. C3, C2, and C1 Truth Table
C3
0
0
0
0
1
1
1
1
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
NOTE:
NOT ALL MUXOUT MODES SHOWN REFER TO MUX REGISTER
SERIAL DATA OUTPUT
R DIVIDER OUTPUT
N DIVIDER OUTPUT
OUT
OUT
TIMER OUTPUTS
and Lock Detect
can be programmed to provide a digital lock detect
Control Bits
LOGIC HIGH
LOGIC LOW
C2
0
0
1
1
0
0
1
1
Figure 27. MUX
C1
0
1
0
1
0
1
0
1
MUX
OUT
Name
FRAC/INT
MOD/R
Phase
Function
Charge Pump
Power-Down
Mux
Test Mode
CONTROL
Circuit
OUT
section in
ADF4193
DV
D
GND
DD
Register
R0
R1
R2
R3
R4
R5
R6
R7
MUX
OUT
OUT