ADF4193BCPZ Analog Devices Inc, ADF4193BCPZ Datasheet - Page 17

• Manufacturer Part Number: ADF4193BCPZ
• Description: IC PLL FREQ SYNTHESIZER 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4193BCPZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 3.5GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Frequency-max: 3.5GHz
• Pll Type: Frequency Synthesis
• Frequency: 3.5GHz
• Supply Current: 24mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 32
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4193EBZ2 - BOARD EVALUATION EB2 FOR ADF4193EVAL-ADF4193EBZ1 - BOARD EVALUATION EB1 FOR ADF4193
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PHASE REGISTER (R2)
12-Bit Phase
The phase word sets the seed value of the Σ-Δ modulator. It can
be programmed to any integer value from 0 to MOD. As the
phase word is swept from 0 to MOD, the phase of the VCO
output sweeps over a 360° range in steps of 360°/MOD.
Note that the phase bits are double buffered. They do not take
effect until the LE of the next write to R0 (FRAC/INT register).
Therefore, if it is desired to change the phase of the VCO output
frequency, it is necessary to rewrite the INT and FRAC values to
R0, following the write to R2.
The output of a fractional-N PLL can settle to any one of the
MOD possible phase offsets with respect to the reference, where
MOD is the fractional modulus.
DB15
0
DB14
P12
DB13
P11
P12
0
0
0
.
.
.
1
1
1
1
DB12
P10
P11
0
0
0
.
.
.
1
1
1
1
DB11
P9
P10
0
0
0
.
.
.
1
1
1
1
DB10
P8
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
Figure 31. Phase Register (R2)
12-BIT PHASE
DB9
P7
Rev. C | Page 17 of 28
DB8
P3
0
0
0
.
.
.
1
1
1
1
P6
DB7
P5
P2
0
0
1
.
.
.
0
0
1
1
If it is desired to keep the output at the same phase offset with
respect to the reference, each time that particular output
frequency is programmed, then the interval between writes to
R0 must be an integer multiple of MOD reference cycles.
If it is desired to keep the outputs of two ADF4193-based
synthesizers phase coherent with each other, but not necessarily
with their common reference, then it is only required to ensure
that the write to R0 on both chips is performed during the same
reference cycle. The interval between R0 writes in this case does
not have to be an integer multiple of the MOD cycles.
Reserved Bit
The reserved bit, Bit DB15, should be set to 0.
DB6
P4
1
0 = < PHASE VALUE < MOD
P1
0
1
0
.
.
.
0
1
0
1
DB5
P3
PHASE VALUE
0
1
2
.
.
.
4092
4093
4094
4095
DB4
P2
DB3
P1
1
C3 (0)
DB2
CONTROL
C2 (1)
BITS
DB1
C1 (0)
DB0
ADF4193