ADF4193BCPZ Analog Devices Inc, ADF4193BCPZ Datasheet - Page 12

• Manufacturer Part Number: ADF4193BCPZ
• Description: IC PLL FREQ SYNTHESIZER 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4193BCPZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 3.5GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Frequency-max: 3.5GHz
• Pll Type: Frequency Synthesis
• Frequency: 3.5GHz
• Supply Current: 24mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 32
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4193EBZ2 - BOARD EVALUATION EB2 FOR ADF4193EVAL-ADF4193EBZ1 - BOARD EVALUATION EB1 FOR ADF4193
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADF4193
The value of MOD is chosen to give the desired channel step
with the available reference frequency. Thereafter, program the
INT and FRAC words for the desired RF output frequency. See
the Worked Example section for more information.
PFD and Charge Pump
The PFD takes inputs from the R divider and N divider and
produces up and down outputs with a pulse width difference
proportional to the phase difference between the inputs. The
charge pump outputs a net up or down current pulse of a width
equal to this difference, to pump up or pump down the voltage
that is integrated onto the loop filter, which in turn increases or
decreases the VCO output frequency. If the N divider phase lags
the R divider phase, a net up current pulse is produced that
increases the VCO frequency (and thus the phase). If the N
divider phase leads the R divider edge, then a net down pulse is
produced to reduce the VCO frequency and phase. Figure 23 is
a simplified schematic of the PFD and charge pump. The charge
pump is made up of an array of 64 identical cells, each of which
is fully differential. All 64 cells are active during fast lock, but
only one is active during normal operation. Because a single-
ended control voltage is required to tune the VCO, an on-chip,
differential-to-single-ended amplifier is provided for this purpose.
In addition, because the phase-lock loop only controls the
differential voltage generated across the charge pump outputs,
an internal common-mode feedback (CMFB) loop biases the
charge pump outputs at a common-mode voltage of approximately
2 V.
Differential Charge Pump
The charge pump cell (see Figure 24) has a fully differential
design for best up-to-down current matching. Good matching
is essential to minimize the phase offset created when switching
the charge pump current from its high value (in fast lock mode)
to its nominal value (in normal mode).
Figure 23. PFD and Differential Charge Pump Simplified Schematic
R DIVIDER
N DIVIDER
D
D
CLR
CLR
Q
Q
CHARGE
EN[64:1]
ARRAY
PUMP
[64:1]
CMFB
CP
CP
OUT+
OUT–
Rev. C | Page 12 of 28
To pump up, the up switches are on and PMOS current is
sourced out through CP
external loop filter capacitors connected to CP
the NMOS current sink on CP
external loop filter capacitors connected to CP
the differential voltage between CP
To pump down, PMOS current sources out through CP
NMOS current sinks in through CP
(CP
down matching is improved by an order of magnitude over the
conventional single-ended charge pump that depended on the
matching of two different device types. The up/down matching
in this structure depends on how a PMOS matches a PMOS and
an NMOS matches an NMOS.
Fast Lock Timeout Counters
Timeout counters, clocked at one quarter the PFD reference
frequency, are provided to precisely control the fast locking
operation (see Figure 25). Whenever a new frequency is
programmed, the fast lock timers start and the PLL locks into
wide BW mode with the 64 identical 100 μA charge pump cells
active (6.4 mA total). When the ICP counter times out, the
charge pump current is reduced to 1× by deselecting cells in
binary steps over the next six timer clock cycles, until just one
100 μA cell is active. The charge pump current switching from
6.4 mA to 100 μA equates to an 8-to-1 change in loop band-
width. The loop filter must be changed to ensure stability when
this happens. That is the job of the SW1, SW2, and SW3 switches.
The application circuit (shown in Figure 36) shows how they
can be used to reconfigure the loop filter time constants. The
application circuits close to short out external loop filter resistors
during fast lock and open when their counters time out to restore
the filter time constants to their normal values for the 100 μA
charge pump current. Because it takes six timer clock cycles to
reduce the charge pump current to 1×, it is recommended that
both switch timers be programmed to the value of the ICP
timer + 7.
Figure 24. Differential Charge Pump Cell with External Loop Filter Components
OUT+
, CP
OUT−
DOWN
UP
) differential voltage. The charge pump up/
N
P
CP
OUT+
OUT+
; this increases the voltage on the
V
V
BIAS
BIAS
OUT−
P
N
decreases the voltage on the
C
OUT+
OUT+
POUT–
and CP
, which decreases the
P
N
OUT+
OUT−
DOWN
UP
OUT−
. Similarly,
. Therefore,
increases.
OUT−
and