MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 94

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Clock Generator Module (CGM)
VCO clock frequency is corrupt, and appropriate precautions should be taken. If the application is not
frequency sensitive, interrupts should be disabled to prevent PLL interrupt service routines from impeding
software performance or from exceeding stack limitations.
6.7 Special Modes
The WAIT instruction puts the MCU in low power-consumption standby modes.
6.7.1 Wait Mode
The WAIT instruction does not affect the CGM. Before entering wait mode, software can disengage and
turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL) to save power.
Less power-sensitive applications can disengage the PLL without turning it off, so that the PLL clock is
immediately available at WAIT exit. This would be the case also when the PLL is to wake the MCU from
wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost.
6.7.2 Stop Mode
The STOP instruction disables the PLL analog circuits and no clock will be driven out of the VCO.
When entering stop mode with the VCO clock (CGMPCLK) selected, before executing the STOP
instruction:
On exit from stop mode:
6.7.3 CGM During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write the PLL control register during the break state without affecting
the PLLF bit.
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1. Set the oscillator stop mode enable bit (STOP_XCLKEN in CONFIG2) if continuos clock is required
2. Clear the BCS bit to select CGMXCLK as CGMOUT.
1. Set the PLLON bit if cleared before entering stop mode.
2. Wait for PLL to lock by checking the LOCK bit.
3. Set BCS bit to select CGMPCLK as CGMOUT.
in stop mode.
Software can select the CGMPCLK divided by two as the CGMOUT source
even if the PLL is not locked (LOCK = 0). Therefore, software should make
sure the PLL is locked before setting the BCS bit.
MC68HC908AP Family Data Sheet, Rev. 4
7.7.3 SIM Break Flag Control
NOTE
Register.)
Freescale Semiconductor