MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 217

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

13.6 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI
configured as a master, a queued data byte is transmitted immediately after the previous transmission
has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready
to accept new data. Write to the transmit data register only when the SPTE bit is high.
the timing associated with doing back-to-back transmissions with the SPI (SPSCK has CPHA: CPOL =
1:0).
Freescale Semiconductor
SPSCK CYCLE
CPHA = 1
CPHA = 0
NUMBER
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
SPSCK
SPSCK
MOSI
BUS
BUS
BUS
BUS
BUS
Figure 13-7. Transmission Start Delay (Master)
TO SPDR
TO SPDR
TO SPDR
WRITE
WRITE
WRITE
TO SPDR
TO SPDR
WRITE
WRITE
EARLIEST
EARLIEST
EARLIEST
EARLIEST
MC68HC908AP Family Data Sheet, Rev. 4
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
LATEST
SPSCK = INTERNAL CLOCK ÷ 128;
SPSCK = INTERNAL CLOCK ÷ 32;
SPSCK = INTERNAL CLOCK ÷ 8;
128 POSSIBLE START POINTS
32 POSSIBLE START POINTS
8 POSSIBLE START POINTS
SPSCK = INTERNAL CLOCK ÷ 2;
INITIATION DELAY
2 POSSIBLE START POINTS
MSB
1
BIT 6
2
LATEST
LATEST
LATEST
Queuing Transmission Data
BIT 5
3
Figure 13-8
shows
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