MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 225
MC908AP32CFBE
Manufacturer Part Number
MC908AP32CFBE
Description
Manufacturer
Freescale
Datasheet
1.MC908AP32CFBE.pdf
(324 pages)
Specifications of MC908AP32CFBE
Cpu Family
HC08
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
SCI/SPI
Total Internal Ram Size
2KB
# I/os (max)
32
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PQFP
Program Memory Type
Flash
Program Memory Size
32KB
Lead Free Status / RoHS Status
Compliant
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13.12.4 SS (Slave Select)
The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a
slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission.
(See
toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low
between transmissions for the CPHA = 1 format. See
When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as
a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can
still prevent the state of the SS from creating a MODF error. (See
Register.)
When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to
prevent multiple masters from driving MOSI and SPSCK. (See
the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit
is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data
direction register of the shared I/O port. With MODFEN high, it is an input-only pin to the SPI regardless
of the state of the data direction register of the shared I/O port.
The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and
reading the port data register. (See
Freescale Semiconductor
13.5 Transmission
MASTER SS
SPE
MISO/MOSI
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a
high-impedance state. The slave SPI ignores all incoming SPSCK clocks,
even if it was already in the middle of a transmission.
Note 1. X = Don’t care
0
1
1
1
SLAVE SS
SLAVE SS
CPHA = 0
CPHA = 1
SPMSTR
Formats.) Since it is used to indicate the start of a transmission, the SS must be
X
0
1
1
(1)
MODFEN
MC68HC908AP Family Data Sheet, Rev. 4
Figure 13-12. CPHA/SS Timing
BYTE 1
Table
Table 13-3. SPI Configuration
X
X
0
1
13-3.)
Master without MODF
SPI Configuration
Master with MODF
NOTE
Not enabled
Slave
Figure
BYTE 2
13-12.
13.7.2 Mode Fault
13.13.2 SPI Status and Control
General-purpose I/O;
General-purpose I/O;
State of SS Logic
SS ignored by SPI
SS ignored by SPI
Input-only to SPI
Input-only to SPI
BYTE 3
Error.) For the state of
I/O Signals
223
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