MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 170
MC908AP32CFBE
Manufacturer Part Number
MC908AP32CFBE
Description
Manufacturer
Freescale
Datasheet
1.MC908AP32CFBE.pdf
(324 pages)
Specifications of MC908AP32CFBE
Cpu Family
HC08
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
SCI/SPI
Total Internal Ram Size
2KB
# I/os (max)
32
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PQFP
Program Memory Type
Flash
Program Memory Size
32KB
Lead Free Status / RoHS Status
Compliant
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Serial Communications Interface Module (SCI)
WAKE — Wakeup Condition Bit
ILTY — Idle Line Type Bit
PEN — Parity Enable Bit
PTY — Parity Bit
170
This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most
significant bit position of a received character or an idle condition on the RxD pin. Reset clears the
WAKE bit.
This read/write bit determines when the SCI starts counting logic 1s as idle character bits. The
counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then
a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning
the count after the stop bit avoids false idle character recognition, but requires properly synchronized
transmissions. Reset clears the ILTY bit.
This read/write bit enables the SCI parity function. (See
inserts a parity bit in the most significant bit position. (See
This read/write bit determines whether the SCI generates and checks for odd parity or even parity.
(See
1 = Address mark wakeup
0 = Idle line wakeup
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
1 = Parity function enabled
0 = Parity function disabled
1 = Odd parity
0 = Even parity
Table
11-5.) Reset clears the PTY bit.
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
M
0
1
0
0
1
1
Control Bits
PEN:PTY
0X
0X
10
11
10
11
Table 11-5. Character Format Selection
MC68HC908AP Family Data Sheet, Rev. 4
Start
Bits
1
1
1
1
1
1
Data
Bits
NOTE
8
9
7
7
8
8
Character Format
Table
Parity
None
None
Even
Even
Odd
Odd
Figure
11-5.) When enabled, the parity function
11-3.) Reset clears the PEN bit.
Stop
Bits
1
1
1
1
1
1
Character
Length
10 bits
11 bits
10 bits
10 bits
11 bits
11 bits
Freescale Semiconductor
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