MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 295

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

21.4.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from
the return address on the stack if SBSW is set. (see
the BW bit by writing logic 0 to it.
21.4.2 Stop Mode
A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register.
21.5 Break Module Registers
These registers control and monitor operation of the break module:
21.5.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module enable and status bits.
BRKE — Break Enable Bit
BRKA — Break Active Bit
Freescale Semiconductor
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This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic
0 to bit 7. Reset clears the BRKE bit.
This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to
BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
1 = (When read) Break address match
0 = (When read) No break address match
Break status and control register (BRKSCR)
Break address register high (BRKH)
Break address register low (BRKL)
SIM break status register (SBSR)
SIM break flag control register (SBFCR)
Address:
Reset:
Read:
Write:
Figure 21-3. Break Status and Control Register (BRKSCR)
$FE0E
BRKE
Bit 7
0
= Unimplemented
BRKA
6
0
MC68HC908AP Family Data Sheet, Rev. 4
5
0
0
4
0
0
Chapter 7 System Integration Module
3
0
0
2
0
0
1
0
0
Break Module Registers
Bit 0
0
0
(SIM)) Clear
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