MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 201
MC908AP32CFBE
Manufacturer Part Number
MC908AP32CFBE
Description
Manufacturer
Freescale
Datasheet
1.MC908AP32CFBE.pdf
(324 pages)
Specifications of MC908AP32CFBE
Cpu Family
HC08
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
SCI/SPI
Total Internal Ram Size
2KB
# I/os (max)
32
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PQFP
Program Memory Type
Flash
Program Memory Size
32KB
Lead Free Status / RoHS Status
Compliant
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RE — Receiver Enable Bit
RWU — Receiver Wakeup Bit
SBK — Send Break Bit
12.9.3 IRSCI Control Register 3
IRSCI control register 3:
Freescale Semiconductor
Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not
affect receiver interrupt flag bits. Reset clears the RE bit.
This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled.
The WAKE bit in IRSCC1 determines whether an idle input or an address mark brings the receiver out
of the standby state and clears the RWU bit. Reset clears the RWU bit.
Setting and then clearing this read/write bit transmits a break character followed by a logic 1. The logic
1 after the break character guarantees recognition of a valid start bit. If SBK remains set, the
transmitter continuously transmits break characters with no logic 1s between them. Reset clears the
SBK bit.
•
•
1 = Receiver enabled
0 = Receiver disabled
1 = Standby state
0 = Normal operation
1 = Transmit break characters
0 = No break characters being transmitted
Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted
Enables the following interrupts:
–
–
–
–
Receiver overrun interrupts
Noise error interrupts
Framing error interrupts
Parity error interrupts
Address:
Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear.
ENSCI is in SCI control register 1.
Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling
SBK before the preamble begins causes the SCI to send a break character
instead of a preamble.
Reset:
Read:
Write:
$0042
Bit 7
R8
U
Figure 12-14. IRSCI Control Register 3 (IRSCC3)
= Unimplemented
T8
U
6
MC68HC908AP Family Data Sheet, Rev. 4
DMARE
5
0
NOTE
NOTE
NOTE
DMATE
4
0
U = Unaffected
ORIE
3
0
NEIE
2
0
FEIE
1
0
PEIE
Bit 0
0
I/O Registers
201
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