MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 51

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

LVIPWRD — V
LVIREGD — V
SSREC — Short Stop Recovery Bit
STOP — STOP Instruction Enable Bit
COPD — COP Disable Bit
Freescale Semiconductor
LVIPWRD disables the V
LVIREGD disables the V
SSREC enables the CPU to exit stop mode with a delay of 32 ICLK cycles instead of a 4096 ICLK
cycle delay.
STOP enables the STOP instruction.
COPD disables the COP module. (See
1 = V
0 = V
1 = V
0 = V
1 = Stop mode recovery after 32 ICLK cycles
0 = Stop mode recovery after 4096 ICLK cycles
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
1 = COP module disabled
0 = COP module enabled
DD
DD
REG
REG
LVI circuit disabled
LVI circuit enabled
If LVIPWRD=1 and LVIREGD=1, set LVIRSTD=1 before entering stop
mode.
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
When the LVI is disabled in stop mode (LVISTOP=0), the system
stabilization time for long stop recovery (4096 ICLK cycles) gives a delay
longer than the LVI’s turn-on time. There is no period where the MCU is not
protected from a low power condition. However, when using the short stop
recovery configuration option, the 32 ICLK delay is less than the LVI’s
turn-on time and there exists a period in start-up where the LVI is not
protecting the MCU.
REG
DD
LVI circuit disabled
LVI circuit enabled
LVI Circuit Disable Bit
LVI Circuit Disable Bit
REG
DD
LVI circuit. (See
LVI circuit. (See
MC68HC908AP Family Data Sheet, Rev. 4
Chapter 19 Computer Operating Properly
Chapter 20 Low-Voltage Inhibit
NOTE
NOTE
Chapter 20 Low-Voltage Inhibit
Configuration Register 1 (CONFIG1)
(LVI).)
(LVI).)
(COP).)
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