MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 143
MC908AP32CFBE
Manufacturer Part Number
MC908AP32CFBE
Description
Manufacturer
Freescale
Datasheet
1.MC908AP32CFBE.pdf
(324 pages)
Specifications of MC908AP32CFBE
Cpu Family
HC08
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
SCI/SPI
Total Internal Ram Size
2KB
# I/os (max)
32
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PQFP
Program Memory Type
Flash
Program Memory Size
32KB
Lead Free Status / RoHS Status
Compliant
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To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
9.8 I/O Signals
Port B shares four of its pins with the TIM. The four TIM channel I/O pins are T1CH0, T1CH1, T2CH0,
and T2CH1 as described in
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
T1CH0 and T2CH0 can be configured as buffered output compare or buffered PWM pins.
9.9 I/O Registers
These I/O registers control and monitor operation of the TIM:
9.9.1 TIM Status and Control Register
The TIM status and control register (TSC):
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
•
TIM status and control register (TSC)
TIM counter registers (TCNTH:TCNTL)
TIM counter modulo registers (TMODH:TMODL)
TIM channel status and control registers (TSC0, TSC1)
TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L)
Enables TIM overflow interrupts
Flags TIM overflows
Stops the TIM counter
Resets the TIM counter
Prescales the TIM counter clock
Address: T1SC, $0020 and T2SC, $002B
References to either timer 1 or timer 2 may be made in the following text by
omitting the timer number. For example, TSC may generically refer to both
T1SC AND T2SC.
Reset:
Read:
Write:
Bit 7
TOF
0
0
Figure 9-4. TIM Status and Control Register (TSC)
9.3 Pin Name
= Unimplemented
TOIE
6
0
MC68HC908AP Family Data Sheet, Rev. 4
TSTOP
Conventions.
5
1
NOTE
TRST
4
0
0
3
0
0
PS2
2
0
PS1
1
0
Bit 0
PS0
0
I/O Signals
143
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