MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 205

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

NF — Receiver Noise Flag Bit
FE — Receiver Framing Error Bit
PE — Receiver Parity Error Bit
12.9.5 IRSCI Status Register 2
IRSCI status register 2 contains flags to signal the following conditions:
BKF — Break Flag Bit
Freescale Semiconductor
This clearable, read-only bit is set when the SCI detects noise on the RxD pin. NF generates an SCI
error CPU interrupt request if the NEIE bit in IRSCC3 is also set. Clear the NF bit by reading IRSCS1
and then reading the IRSCDR. Reset clears the NF bit.
This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error
CPU interrupt request if the FEIE bit in IRSCC3 also is set. Clear the FE bit by reading IRSCS1 with
FE set and then reading the IRSCDR. Reset clears the FE bit.
This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates
an SCI error CPU interrupt request if the PEIE bit in IRSCC3 is also set. Clear the PE bit by reading
IRSCS1 with PE set and then reading the IRSCDR. Reset clears the PE bit.
•
•
This clearable, read-only bit is set when the SCI detects a break character on the RxD pin. In IRSCS1,
the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in IRSCC3 is cleared.
BKF does not generate a CPU interrupt request. Clear BKF by reading IRSCS2 with BKF set and then
reading the IRSCDR. Once cleared, BKF can become set again only after logic 1s again appear on
the RxD pin followed by another break character. Reset clears the BKF bit.
1 = Noise detected
0 = No noise detected
1 = Framing error detected
0 = No framing error detected
1 = Parity error detected
0 = No parity error detected
1 = Break character detected
0 = No break character detected
Break character detected
Incoming data
Address:
Reset:
Read:
Write:
$0044
Bit 7
0
Figure 12-17. IRSCI Status Register 2 (IRSCS2)
= Unimplemented
6
0
MC68HC908AP Family Data Sheet, Rev. 4
5
0
4
0
3
0
2
0
BKF
1
0
Bit 0
RPF
0
I/O Registers
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