MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 203

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

12.9.4 IRSCI Status Register 1
SCI status register 1 contains flags to signal these conditions:
SCTE — SCI Transmitter Empty Bit
TC — Transmission Complete Bit
SCRF — SCI Receiver Full Bit
IDLE — Receiver Idle Bit
Freescale Semiconductor
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This clearable, read-only bit is set when the IRSCDR transfers a character to the transmit shift register.
SCTE can generate an SCI transmitter CPU interrupt request. When the SCTIE bit in IRSCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by
reading IRSCS1 with SCTE set and then writing to IRSCDR. Reset sets the SCTE bit.
This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being
transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in IRSCC2 is also
set. TC is automatically cleared when data, preamble or break is queued and ready to be sent. There
may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the
transmission actually starting. Reset sets the TC bit.
This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data
register. SCRF can generate an SCI receiver CPU interrupt request. When the SCRIE bit in IRSCC2
is set, SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading
IRSCS1 with SCRF set and then reading the IRSCDR. Reset clears SCRF.
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input.
IDLE generates an SCI receiver CPU interrupt request if the ILIE bit in IRSCC2 is also set. Clear the
IDLE bit by reading IRSCS1 with IDLE set and then reading the IRSCDR. After the receiver is enabled,
1 = IRSCDR data transferred to transmit shift register
0 = IRSCDR data not transferred to transmit shift register
1 = No transmission in progress
0 = Transmission in progress
1 = Received data available in IRSCDR
0 = Data not available in IRSCDR
Transfer of IRSCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data to IRSCDR complete
Receiver input idle
Receiver overrun
Noisy data
Framing error
Parity error
Address:
Reset:
Read:
Write:
$0043
SCTE
Bit 7
1
Figure 12-15. IRSCI Status Register 1 (IRSCS1)
= Unimplemented
TC
6
1
MC68HC908AP Family Data Sheet, Rev. 4
SCRF
5
0
IDLE
4
0
OR
3
0
NF
2
0
FE
1
0
Bit 0
PE
0
I/O Registers
203