MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 81

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

6.3.1 Oscillator Module
The oscillator module provides two clock outputs CGMXCLK and CGMRCLK to the CGM module.
CGMXCLK when selected, is driven to SIM module to generate the system bus clock. CGMRCLK is used
by the phase-lock-loop to provide a higher frequency system bus clock. The oscillator module also
provides the reference clock for the timebase module (TBM). See
oscillator circuit description. See
6.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending
on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes
either automatically or manually.
6.3.3 PLL Circuits
The PLL consists of these circuits:
Freescale Semiconductor
$0036
$0037
$0038
$0039
$003A
$003B
Addr.
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
•
•
•
•
Voltage-controlled oscillator (VCO)
Reference divider
Frequency pre-scaler
Modulo VCO frequency divider
PLL VCO Range Select
PLL Bandwidth Control
PLL Reference Divider
Register Name
PLL Control Register
PLL Multiplier Select
PLL Multiplier Select
Select Register
Register High
Register Low
Register
Register
(PBWC)
(PMSH)
(PMRS)
(PMDS)
(PMSL)
(PTCL)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Figure 6-2. CGM I/O Register Summary
Chapter 10 Timebase Module (TBM)
MC68HC908AP Family Data Sheet, Rev. 4
PLLIE
AUTO
MUL7
VRS7
Bit 7
0
0
0
0
0
0
0
0
= Unimplemented
LOCK
MUL6
VRS6
PLLF
6
0
0
0
0
1
1
0
0
PLLON
MUL5
VRS5
ACQ
5
1
0
0
0
0
0
0
0
MUL4
VRS4
BCS
4
0
0
0
0
0
0
0
0
0
Chapter 5 Oscillator (OSC)
MUL11
for detailed description on TBM.
MUL3
RDS3
PRE1
VRS3
R
3
0
0
0
0
0
0
0
= Reserved
MUL10
MUL2
RDS2
PRE0
VRS2
2
0
0
0
0
0
0
0
Functional Description
VPR1
MUL9
MUL1
VRS1
RDS1
1
0
0
0
0
0
0
0
for detailed
VPR0
MUL8
MUL0
VRS0
RDS0
Bit 0
R
0
0
0
0
1
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