MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 233

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

14.5 Multi-Master IIC Bus Protocol
Normally a standard communication is composed of four parts:
These are described briefly in the following sections and illustrated in
14.5.1 START Signal
When the bus is free, (i.e. no master device is engaging the bus — both SCL and SDA lines are at logic
high) a master may initiate communication by sending a START signal. As shown in
START signal is defined as a high to low transition of SDA while SCL is high. This signal denotes the
beginning of a new data transfer (each data transfer may contain several bytes of data) and wakes up all
slaves.
14.5.2 Slave Address Transmission
The first byte transferred immediately after the START signal is the slave address transmitted by the
master. This is a 7-bit calling address followed by a R/W-bit. The R/W-bit dictates to the slave the desired
direction of the data transfer. A logic 0 indicates that the master wishes to transmit data to the slave; a
logic 1 indicates that the master wishes to receive data from the slave.
Freescale Semiconductor
1. START signal,
2. slave address transmission,
3. data transfer, and
4. STOP signal.
SDA
SDA
SCL
SCL
START
START
signal
signal
MSB
MSB
1
1
Figure 14-2. Multi-Master IIC Bus Transmission Signal Diagram
1
1
0
0
0
0
0
0
MC68HC908AP Family Data Sheet, Rev. 4
0
0
1
1
LSB
9th clock pulse
LSB
1
1
ACK
ACK
Repeated
START
signal
MSB
MSB
1
1
1
1
Data must be stable
when SCL is HIGH
0
0
Figure
1
1
14-2.
Multi-Master IIC Bus Protocol
0
0
0
0
Figure
1
1
9th clock pulse
LSB
LSB
1
1
No ACK
No ACK
14-2, a
STOP
signal
STOP
signal
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