MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 239

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

MMRW — MMIIC Master Read/Write
MMCRCEF — MMIIC CRC Error Flag
14.6.4 MMIIC Status Register (MMSR)
MMRXIF — MMIIC Receive Interrupt Flag
MMTXIF — MMIIC Transmit Interrupt Flag
MMATCH — MMIIC Address Match Flag
Freescale Semiconductor
This bit is transmitted out as bit 0 of the calling address when the module sets the MMAST bit to enter
master mode. The MMRW bit determines the transfer direction of the data bytes that follows. When it
is "1", the module is in master receive mode. When it is "0", the module is in master transmit mode.
Reset clears this bit.
This flag is set when a CRC error is detected, and cleared when no CRC error is detected. The
MMCRCEF is only meaningful after receiving a PEC data. This flag is unaffected by reset.
This flag is set after the data receive register (MMDRR) is loaded with a new received data. Once the
MMDRR is loaded with received data, no more received data can be loaded to the MMDRR register
until the CPU reads the data from the MMDRR to clear MMRXBF flag. MMRXIF generates an interrupt
request to CPU if the MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or by reset;
or when the MMEN = 0.
This flag is set when data in the data transmit register (MMDTR) is downloaded to the output circuit,
and that new data can be written to the MMDTR. MMTXIF generates an interrupt request to CPU if the
MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or when the MMEN = 0.
This flag is set when the received data in the data receive register (MMDRR) is a calling address which
matches with the address or its extended addresses (MMEXTAD = 1) specified in the address register
(MMADR). The MMATCH flag is set at the 9th clock of the calling address and will be cleared on the
9th clock of the next receiving data. Note: slave transmits do not clear MMATCH.
1 = Master mode receive
0 = Master mode transmit
1 = CRC error detected on PEC byte
0 = No CRC error detected on PEC byte
1 = New data in data receive register (MMDRR)
0 = No data received
1 = Data transfer completed
0 = Data transfer in progress
1 = Received address matches MMADR
0 = Received address does not match
Address:
Reset:
Read:
Write:
MMRXIF
$004B
Bit 7
0
0
Figure 14-7. MMIIC Status Register (MMSR)
= Unimplemented
MMTXIF
0
0
6
MC68HC908AP Family Data Sheet, Rev. 4
MMATCH
5
0
MMSRW
4
0
MMRXAK
3
1
MMCRCBF
2
0
MMTXBE
1
1
MMRXBF
MMIIC I/O Registers
Bit 0
0
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