MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 270

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Input/Output (I/O) Ports
PTD[7:0] — Port D Data Bits
KBI7–KBI0 — Keyboard Interrupt Inputs
16.5.2 Data Direction Register D (DDRD)
Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to
a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer.
DDRD[7:0] — Data Direction Register D Bits
Figure 16-14
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a
logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
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These read/write bits are software programmable. Data direction of each port D pin is under the control
of the corresponding bit in data direction register D. Reset has no effect on port D data.
The keyboard interrupt enable bits, KBIE[7:0], in the keyboard interrupt enable register (KBIER),
enable the port D pins as external interrupt pins. See
These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
shows the port D I/O logic.
Address:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Reset:
Read:
Write:
READ DDRD ($0007)
WRITE DDRD ($0007)
WRITE PTD ($0003)
READ PTD ($0003)
DDRD7
$0007
Bit 7
0
Figure 16-13. Data Direction Register D (DDRD)
DDRD6
6
0
MC68HC908AP Family Data Sheet, Rev. 4
RESET
Figure 16-14. Port D I/O Circuit
DDRD5
5
0
NOTE
DDRD4
DDRDx
PTDx
4
0
Chapter 18 Keyboard Interrupt Module
DDRD3
3
0
# PTD7–PTD0 have schmitt trigger inputs.
DDRD2
2
0
KBIEx
DDRD1
1
0
Freescale Semiconductor
DDRD0
PTDx
Bit 0
0
#
(KBI).