MC908AP32CFBE Freescale, MC908AP32CFBE Datasheet - Page 50

• Manufacturer Part Number: MC908AP32CFBE
• Manufacturer: Freescale

Specifications of MC908AP32CFBE

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Configuration & Mask Option Registers (CONFIG & MOR)
3.2 Functional Description
The configuration registers and the mask option register are used in the initialization of various options.
These two types of registers are configured differently:
The configuration registers can be written once after each reset. All of the configuration register bits are
cleared during reset. Since the various options affect the operation of the MCU, it is recommended that
these registers be written immediately after reset. The configuration registers are located at $001D and
$001F. The configuration registers may be read at anytime.
The mask option register (MOR) is used for selecting one of the three clock options for the MCU. The
MOR is a byte located in FLASH memory, and is written to by a FLASH programming routine.
3.3 Configuration Register 1 (CONFIG1)
COPRS — COP Rate Select Bit
LVISTOP — LVI Enable in Stop Mode Bit
LVIRSTD — LVI Reset Disable Bit
50
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COPRS selects the COP time out period. Reset clears COPRS. (See
Properly
When the LVIPWRD or LVIREGD bit is clear, setting the LVISTOP bit enables the LVI to operate
during stop mode. Reset clears LVISTOP. (See
LVIRSTD disables the reset signal from the LVI module. (See
1 = COP time out period = 2
0 = COP time out period = 2
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
1 = LVI module resets disabled
0 = LVI module resets enabled
Configuration registers — Write-once registers after reset
Mask option register — FLASH register (write by programming)
(COP).)
Address:
The CONFIG registers are not in the FLASH memory but are special
registers containing one-time writable latches after each reset. Upon a
reset, the CONFIG registers default to predetermined settings as shown in
Figure 3-2
Reset:
Read:
Write:
If LVISTOP=0, set LVIRSTD=1 before entering stop mode.
COPRS
$001F
Bit 7
0
and
Figure 3-2. Configuration Register 1 (CONFIG1)
Figure
LVISTOP
6
0
MC68HC908AP Family Data Sheet, Rev. 4
13
18
– 2
– 2
3-3.
LVIRSTD
4
4
ICLK cycles
ICLK cycles
5
0
LVIPWRD
NOTE
NOTE
Chapter 20 Low-Voltage Inhibit
4
0
LVIREGD
3
0
Chapter 20 Low-Voltage Inhibit
SSREC
2
0
Chapter 19 Computer Operating
STOP
1
0
Freescale Semiconductor
(LVI).)
COPD
Bit 0
0
(LVI).)