FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 75

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

follows:
-
-
*Note: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.
BAUD RATE
interrupt mode, the IIR is not affected
DESIRED
Bit 0=1 as long as there is one byte in the
RCVR FIFO.
Bits 1 to 4 specify which error(s) have
occurred. Character error status is
handled the same way as when in the
since EIR bit 2=0.
115200
230400
460800
19200
38400
57600
134.5
Table 33 - Baud Rates Using 1.8462 MHz Clock for <= 38.4K; Using 1.8432MHz Clock
1200
1800
2000
2400
3600
4800
7200
9600
110
150
300
600
for 115.2k ; Using 3.6864MHz Clock for 230.4k; Using 7.3728 MHz Clock for 460.8k
50
75
GENERATE 16X CLOCK
DIVISOR USED TO
32770
32769
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
1
BETWEEN DESIRED AND ACTUAL*
75
PERCENT ERROR DIFFERENCE
-
-
There is no trigger level reached or timeout
condition indicated in the FIFO Polled Mode,
however, the RCVR and XMIT FIFOs are still
fully capable of holding characters.
shift register are empty.
empty.
Bit 6 indicates that both the XMIT FIFO and
Bit 7 indicates whether there are any
errors in the RCVR FIFO.
0.001
0.004
0.005
0.030
0.16
0.16
0.16
0.16
-
-
-
-
-
-
-
-
-
-
-
-
-
BIT 7 OR 6
CRxx:
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1