FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 195

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Note:
NAME
t10
t11
t12
t13
t15
t19
t20
t21
t22
t23
t2
t3
t4
t5
t8
FIGURE 19B - EPP 1.7 DATA OR ADDRESS READ CYCLE PARAMETERS
WRITE is controlled by setting the PDIR bit to "1" in the control register before performing an
EPP Read.
nIOR Deasserted to Command Deasserted
nWAIT Asserted to IOCHRDY Deasserted
Command Deasserted to PDATA Hi-Z
Command Asserted to PDATA Valid
nIOR Asserted to IOCHRDY Asserted
nWAIT Deasserted to IOCHRDY Deasserted
IOCHRDY Deasserted to nIOR Deasserted
nIOR Deasserted to SDATA High-Z (Hold Time)
PDATA Valid to SDATA Valid
Time Out
Ax Valid to nIOR Asserted
nIOR Deasserted to Ax Invalid
Command Deasserted to nWAIT Deasserted
nIOR Deasserted to nIOW or nIOR Asserted
nIOR Asserted to Command Asserted
DESCRIPTION
195
MIN
10
40
10
40
0
0
0
0
0
0
TYP
MAX
50
40
24
50
40
40
12
55
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s