FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 201

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

PAGE
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167
10
1
1
4
8
Real Time Clock
IDE Interface
Pin Configuration
Bios Buffers
Block Diagram
Bios Buffer
Table 46
Second Paragraph
General Purpose Read/Write
8042 Keyboard Controller
Port Definition and Description
RTC Interrupt
UIP/DV 2-0/RS 3-0
Power Management
Table 62/Bit[7]
OSC, Bits[3:2]
FDD Option Register, Bits[7:6]
FDD Type Register, Bits[5:4] and [7:6]
Table 74, GP20, Bit[4]
Table 74
Sequence Operation
Items 3 and 4
SECTION/FIGURE/ENTRY
FDC37C93x ERRATA SHEET
Pin
"nROMDIR"
"nROMOE"
"nROMDIR"
"nGPRD"
"nGPA", "nROMOE" changed
to "nROMDIR"
"nROMOE"
"nROMDIR"
"GP Read Strobe" changed to
"GP Address Decoder"
"when PWRGD is active.
When PWRGD is inactive,
OSC is off and BRG Clock is
disabled (default)" was re-
moved.
"RESET OUT (Active Low)"
removed, see italicized text
First Paragraph Removed
"typ" changed to "max"
Step 2 was removed
See Italicized Text
See Italicized Text
See Italicized Text
See Italicized Text
See Italicized Text
See Italicized Text
See Italicized Text
See Italicized Text
See Italicized Text
See Italicized Text
See Italicized Text
#120
CORRECTION
Removed
changed
changed
changed
changed
to
to
to
to
REVISED
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DATE