FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 133

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

REGISTER B (BH)
SET
When the SET bit is a "0", the update functions
normally by advancing the counts once per
second. When the SET bit is a "1", an update
cycle in progress is aborted and the program
may initialize the
without an update occurring in the middle of
initialization. SET is a read/write bit which is
not modified by RESET_DRV or any internal
functions.
PIE
The periodic interrupt enable bit is a read/write
bit which allows the periodic-interrupt flag (PF)
bit in Register C to cause the IRQB port to be
driven low. The program writes a "1" to the PIE
bit in order to receive periodic interrupts at the
rate specified by the RS3 - RS0 bits in Register
A. A zero in PIE blocks IRQB from being
initiated by a periodic interrupt, but the periodic
flag (PF) is still set at the periodic rate. PIE is
not modified
cleared to "0" by a RESET_DRV.
AIE
The alarm interrupt enable bit is a read/write bit,
which when set to a "1" permits the alarm flag
(AF)
alarm interrupt occurs for each second that the
three time bytes equal the three alarm bytes
(including a "don't care" alarm code of binary
11XXXXXX). When the AIE bit is a "0", the AF
bit does not initiate an IRQB signal. The
RESET_DRV port clears AIE to "0". The AIE bit
is not affected by any internal functions.
MSB
SET
b7
bit in Register C to assert
by any internal function, but is
PIE
b6
time
and
AIE
b5
calendar bytes
IRQB.
UIE
b4
An
133
UIE
The update-ended interrupt enable bit is a
read/write bit which enables the update-end flag
(UF)
RESET_DRV port or the SET bit going high
clears the UIE bit.
RES
Reserved - read as zero
DM
The data mode bit indicates whether time and
calendar updates are to use binary or BCD
formats.
processor program and may be read by the
program, but is not modified by any internal
functions or by RESET_DRV. A "1" in DM
signifies binary data, while a "0" in DM specifies
BCD data.
24/12
The 24/12 control bit establishes the format of
the hours byte as either the 24 hour mode if
set to a "1", or the 12 hour mode if cleared to
a "0".
affected by RESET_DRV or any internal
function.
DSE
The daylight savings enable bit is read only and
is always set
daylight savings time option is not available.
RES
b3
bit in Register C to assert IRQB. The
This is a read/write bit which is
The DM bit is written
DM2
b2
to a "0"
24/12
b1
to indicate that the
by
DSE
LSB
b0
the
not