FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet
FDC37C935-QS
Specifications of FDC37C935-QS
Related parts for FDC37C935-QS
FDC37C935-QS Summary of contents
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Plug and Play Compatible Ultra I/O 5 Volt Operation ISA Plug-and-Play Standard (Version 1.0a) Compatible Register Set 8042 Keyboard Controller - 2K Program ROM - 256 Bytes Data RAM - Asynchronous Access to Two Data Registers and One Status Register ...
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FEATURES ........................................................................................................................................1 GENERAL DESCRIPTION..................................................................................................................3 PIN CONFIGURATION.......................................................................................................................4 DESCRIPTION OF PIN FUNCTIONS .................................................................................................5 FUNCTIONAL DESCRIPTION ..........................................................................................................11 SUPER I/O REGISTERS ..................................................................................................................11 HOST PROCESSOR INTERFACE....................................................................................................11 FLOPPY DISK CONTROLLER .........................................................................................................12 FDC INTERNAL REGISTERS...........................................................................................................12 COMMAND SET/DESCRIPTIONS ....................................................................................................36 INSTRUCTION SET .........................................................................................................................40 SERIAL PORT (UART) .....................................................................................................................66 INFRARED INTERFACE...................................................................................................................80 ...
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Relocatable to 480 Different Addresses - 13 IRQ Options - 4 DMA Options - Enhanced Mode - Standard Mode: - IBM PC/XT, PC/AT, and PS/2 Compatible Bidirectional Parallel Port - Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and ...
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GND 1 DRVDEN0 2 DRVDEN1 3 nMTR0 4 nDS1 5 nDS0 6 nMTR1 7 GND 8 nDIR 9 nSTEP 10 nWDATA 11 nWGATE 12 nHDSEL 13 nINDEX 14 nTRK0 15 nWRTPRT 16 FDC37C93x nRDATA 17 nDSKCHG 18 MEDIA_ID1 19 mEDIA_ID0 ...
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PIN NO. NAME PROCESSOR/HOST INTERFACE 72:79 System Data Bus 41:52 System Address Bus 53 Chip Select/SA12 (Active Low)(Note 1) 70 Address Enable (DMA master has bus control) 90 I/O Channel Ready 80 Reset Drive 67:61, Interrupt Requests [1,3:12,14,15] 59:54 (Polarity ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME 13 Head Select (1 = side Step Direction (1 = out ) 10 Step Pulse 18 Disk Change 5,6 Drive Select Lines 7,4 Motor On Lines 16 Write Protected 15 ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME 23 IDE1 Enable 24 IDE1 Chip Select 0 25 IDE1 Chip Select 1 30 IOR Output 31 IOW Output 32:34 Address [2:0] Output 26 IDE1 Interrupt Request 27 IDE2 Chip Select 2/SA13 (Note ...
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PIN NO. 94 Mouse Clock 96 GP I/O; IRQ I/O; IRQ I/O; WD Timer Output /IRRX 99 GP I/O; Power Led output /IRTX 100 GP I/O; GP Address Decode 102 GP I/O; GP Write ...
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Buffer Type Descriptions I Input, TTL compatible. IS Input with Schmitt trigger. I/OD16P Input/Output, 16mA sink, 90uA pull-up. I/O24 Input/Output, 24mA sink, 12mA source. I/O4 Input/Output, 4mA sink, 2mA source O4 Output, 4mA sink, 2mA source. O8SR Output, 8mA sink, ...
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V Vcc (5) Vss (7) DATAIN* SERIAL DATAOUT* EEPROM CLK*, ENABLE* nIDE_ACK nIOR nIOW AEN SA[0:12] HOST SA[13-15] CPU SD[O:7] INTERFACE DRQ[0:3] nDACK[0:3] TC IRQ[1,3-12,14,15] CLOCK RESET_DRV GEN IOCHRDY CLK 1 (14.318) 24CLK CLK0[1:3] 16CLK (14.318) FIGURE 1 - ...
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FUNCTIONAL DESCRIPTION SUPER I/O REGISTERS The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, IDE, serial and parallel ports can ...
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FLOPPY DISK CONTROLLER The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an ...
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STATUS REGISTER A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the FINTR pin and several PS/2 Mode 7 INT nDRV2 PENDING RESET 0 COND. BIT 0 DIRECTION Active high status indicating the direction ...
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PS/2 Model 30 Mode 7 INT DRQ PENDING RESET 0 COND. BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates direction; a logic "1" indicates outward direction. BIT 1 WRITE PROTECT Active high ...
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STATUS REGISTER B (SRB) Address F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 and PS/2 Mode RESET 1 1 COND. BIT 0 MOTOR ENABLE 0 Active ...
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PS/2 Model 30 Mode 7 6 nDRV2 nDS1 RESET N/A 1 COND. BIT 0 nDRIVE SELECT 2 Active low status of the DS2 disk interface output. BIT 1 nDRIVE SELECT 3 Active low status of the DS3 disk interface output. ...
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DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs MOT MOT EN3 EN2 RESET 0 0 COND. BIT 0 and 1 DRIVE SELECT These two ...
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TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE This register is included for 82077 software compatability. The robust digital data separator used in the FDC does not characteristics modified for tape support. The contents of this register are not used internal ...
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Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits are a high impedance. DB7 DB6 REG 3F3 Tri-state Tri-state Enhanced Floppy Mode 2 (OS2) Register 3F3 for ...
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Digital Output Register Bit 1 Bit Note: L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x. Register 3F3 - Drive Type ID Bit 5 0 L0-CRF2 - B1 1 L0-CRF2 - B3 0 L0-CRF2 ...
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DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only used to program the data rate, amount of write precompensation, power down status, and software reset. data rate is programmed Configuration Control Register (CCR) ...
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DRIVE RATE DATA RATE DRT1 DRT0 SEL1 ...
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Table 13 - Default Precompensation Delays PRECOMPENSATION DATA RATE DELAYS 2 Mbps 20 Mbps 41.67 ns 500 Kbps 125 ns 300 Kbps 125 ns 250 Kbps 125 ns *The 2 Mbps data rate is only available if V ...
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MAIN STATUS REGISTER Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any RQM DIO NON DMA BIT ...
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DATA REGISTER (FIFO) Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register. Data transfers are governed by the RQM and DIO bits ...
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DIGITAL INPUT REGISTER (DIR) Address 3F7 READ ONLY This register is read-only in all modes. PC-AT Mode 7 6 DSK CHG RESET N/A N/A COND. BIT UNDEFINED The data bus outputs will remain in ...
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Model 30 Mode 7 6 DSK 0 CHG RESET N/A 0 COND. BITS DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 11 for the settings corresponding to the individual data ...
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CONFIGURATION CONTROL REGISTER (CCR) Address 3F7 WRITE ONLY PC/AT and PS/2 Modes 7 6 RESET N/A N/A COND. BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table ...
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STATUS REGISTER ENCODING During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. BIT NO. SYMBOL NAME 7,6 IC Interrupt Code 5 SE Seek End 4 EC Equipment ...
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Table 16 - Status Register 1 BIT NO. SYMBOL NAME 7 EN End of Cylinder Data Error 4 OR Overrun/ Underrun Data 1 NW Not Writable 0 MA Missing Address Mark DESCRIPTION The ...
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Table 17 - Status Register 2 BIT NO. SYMBOL NAME Control Mark 5 DD Data Error in Data Field 4 WC Wrong Cylinder Bad Cylinder 0 MD Missing Data Address Mark DESCRIPTION Unused. ...
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BIT NO. SYMBOL NAME Write Protected Track Head Address 1,0 DS1,0 Drive Select RESET There are three sources of system reset on the FDC: the RESET pin of the FDC, ...
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This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the DOR becomes a "don't care", (FINTR and DRQ are always valid), TC and DENSEL become active low. Model 30 mode - (IDENT low, MFM ...
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The host reads (writes) from (to) the FIFO until empty (full), then the transfer request goes inactive. The host must be ...
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FDC will continue to complete the sector hardware TC was received. The only difference between these implicit functions and TC is that they return "abnormal ...
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COMMAND SET/DESCRIPTIONS Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, ...
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Table 19 - Description of Command Symbols SYMBOL NAME GAP Alters Gap 2 length when using Perpendicular Mode. GPL Gap Length The Gap 3 size. (Gap 3 is the space between sectors excluding the VCO synchronization field). H/HDS Head Address ...
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Table 19 - Description of Command Symbols SYMBOL NAME N Sector Size Code NCN New Cylinder Number ND Non-DMA Mode Flag OW Overwrite PCN Present Cylinder Number POLL Polling Disable PRETRK Precompensation Start Track Number R Sector Address RCN Relative ...
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Table 19 - Description of Command Symbols SYMBOL NAME Verify command when EC is set. SK Skip Flag When set to 1, sectors containing a deleted data address mark will automatically be skipped during the execution of Read Data. If ...
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PHASE R Command W MT MFM Execution Result INSTRUCTION SET Table 20 - Instruction Set READ DATA DATA BUS D5 ...
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PHASE R Command W MT MFM Execution Result READ DELETED DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DELETED DATA DATA BUS ...
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PHASE R Command W 0 MFM Execution Result READ A TRACK DATA BUS ...
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PHASE R Command W MT MFM Execution Result PHASE R Command Result VERIFY ...
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PHASE R Command W 0 MFM Execution for W Each Sector Repeat Result FORMAT A TRACK DATA BUS ...
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PHASE R Command Execution PHASE R Command Result R R PHASE R Command --- SRT --- W ------ HLT ------ RECALIBRATE ...
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PHASE R Command Result R PHASE R Command Execution PHASE R Command EIS ...
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PHASE R Command W 1 DIR PHASE R/W D7 Command W 0 Execution Result ---- SRT ---- LOCK R 0 EIS EFIFO POLL R RELATIVE SEEK ...
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PHASE R Command W 0 MFM Execution Result READ ID DATA BUS HDS DS1 DS0 ...
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PHASE R Command PHASE R Command W ----- Invalid Codes ----- Result R PHASE R/W D7 Command W LOCK Result returned if the last command that was issued was ...
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DATA TRANSFER COMMANDS All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied ...
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If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette's index hole passes through index detect logic in the drive twice), the FDC sets the IC code ...
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Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 24 - Skip Bit vs. Read Deleted ...
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FINAL SECTOR TRANSFERRED TO MT HEAD HOST Less than EOT 0 0 Equal to EOT Less than EOT 1 Equal to EOT Less than EOT 1 0 Equal to EOT Less than EOT 1 Equal to EOT NC: No Change, ...
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Verify The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read Data command except that no data is transferred to the host. Data is read from the disk and CRC ...
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Format A Track The Format command allows an entire track to be formatted. After a pulse from the IDX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per ...
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Table 27 - Typical Values for Formatting FORMAT SECTOR SIZE 128 128 512 FM 1024 2048 4096 5.25" ... Drives 256 256 512* MFM 1024 2048 4096 ... 128 FM 256 3.5" 512 Drives 256 MFM 512** 1024 GPL1 = ...
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CONTROL COMMANDS Control commands differ from commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. Read ID The Read ID ...
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Seek command - Step to the proper track 2) Sense Interrupt Status command Terminate the Seek command 3) Read ID - Verify head is on proper track 4) Issue Read/Write command. The ...
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Time) defines the time between when the Head Load signal goes high and the read/write Table 29 - Drive Control Delays (ms 500K 0 64 128 256 112 ...
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PRETRK - Pre-Compensation Number. Programmable from track 0 to 255. Defaults to track 0. A "00" selects track 0; "FF" selects track 255. Version The Version command checks to see if the controller is an enhanced type or ...
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Seek, but the host is required to calculate the difference between the current head location and the new (target) head location. This may require the host to issue a Read ID command to ensure that the head is physically ...
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When both GAP and WGATE bits of the PERPENDICULAR MODE COMMAND are both programmed to "0" (Conventional mode), then D0, D1, D2, D3, and D4 can ...
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Table 30 - Effects of WGATE and GAP Bits WGATE GAP MODE 0 0 Conventional 0 1 Perpendicular (500 Kbps Reserved (Conventional Perpendicular (1 Mbps) LOCK In order to protect systems with long DMA latencies against ...
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The FDC37C93x incorporates two full function UARTs. They are compatible NS16450, the 16450 ACE registers and the NS16550A. The UARTS perform serial-to- parallel conversion on received characters and parallel-to-serial conversion on characters. The data rates are independently programmable from 460.8K ...
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RECEIVE BUFFER REGISTER (RB) Address Offset = 0H, DLAB = 0, READ ONLY This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received first. Received data is double ...
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Bit 2 Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self- clearing. Bit 3 Writting to this ...
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Table 32 - Interrupt Control Table FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER BIT BIT BIT BIT PRIORITY LEVEL Highest Second ...
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LINE CONTROL REGISTER (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE This register contains the format information of the serial line. The bit definitions are: Bits 0 and 1 These two bits specify the number of bits in each ...
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Bit 0 This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic "1", the nDTR output is forced to a logic "0". When bit logic "0", the nDTR output is ...
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FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. Bit 3 Framing Error (FE). Bit 3 indicates that the received character did not ...
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Bit 0 Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the last time the MSR was read. Bit 1 Delta Data Set Ready (DDSR). Bit 1 indicates that the ...
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FIFO has reached its programmed trigger level cleared as soon as the FIFO drops below its programmed trigger level. B. The IIR receive data available indication also occurs when the FIFO trigger level is reached. ...
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Bit 0=1 as long as there is one byte in the RCVR FIFO. - Bits specify which error(s) have occurred. Character error status is handled the same way as when in the interrupt mode, the ...
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Table 34 - Reset Function Table REGISTER/SIGNAL Interrupt Enable Register RESET Interrupt Identification Reg. RESET FIFO Control RESET Line Control Reg. RESET MODEM Control Reg. RESET Line Status Reg. RESET MODEM Status Reg. RESET TXD1, TXD2 RESET INTRPT (RCVR errs) ...
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Table 35 - Register Summary for an Individual UART Channel REGISTER ADDRESS* REGISTER NAME ADDR = 0 Receive Buffer Register (Read Only) DLAB = 0 ADDR = 0 Transmitter Holding Register (Write DLAB = 0 Only) ADDR = 1 Interrupt ...
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Table 35 - Register Summary for an Individual UART Channel (continued) BIT 2 BIT 3 Data Bit 2 Data Bit 3 Data Bit 2 Data Bit 3 Enable Enable Receiver Line MODEM Status Status Interrupt Interrupt (ELSI) (EMSI) Interrupt ID ...
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NOTES ON SERIAL PORT OPERATION FIFO MODE OPERATION: GENERAL The RCVR FIFO will hold bytes regardless of which trigger level is selected. TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD ...
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The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. implementations have been provided for the second UART in this chip (logical device 5), IrDA and Amplitude Shift Keyed IR. transmission can use the standard ...
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The FDC37C93x incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information ...
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Table 36 - Parallel Port Connector HOST CONNECTOR PIN NUMBER 1 2 (1) = Compatible Mode (3) = High Speed Mode Note: For the cable interconnection required for ECP support and the ...
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IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES DATA PORT ADDRESS OFFSET = 00H The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. WRITE operation, the Data ...
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BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line ...
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EPP DATA PORT 2 ADDRESS OFFSET = 06H The EPP Data Port 2 is located at an offset of '06H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available ...
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PData bus contains valid information, and the WRITE signal is valid. 6. Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip may begin the termination phase of the cycle The chip ...
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The timer indicates if more than 10usec have elapsed from the start of the EPP cycle (nIOR or nIOW asserted) to the end of the cycle nIOR or nIOW deasserted time-out occurs, the current EPP cycle is ...
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Table 37 - EPP Pin Descriptions EPP SIGNAL EPP NAME TYPE nWRITE nWrite O PD<0:7> Address/Data I/O INTR Interrupt I WAIT nWait I DATASTB nData Strobe O RESET nReset O ADDRSTB nAddress O Strobe PE Paper End I SLCT Printer ...
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EXTENDED CAPABILITIES PARALLEL PORT ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. High performance half-duplex forward and reverse channel Interlocked handshake, for ...
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ISA IMPLEMENTATION STANDARD This specification describes the standard ISA interface to the Extended Capabilities Port (ECP). All ISA devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a ...
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Table 38 - ECP Pin Descriptions NAME TYPE nStrobe O During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). PData 7:0 I/O Contains address or data or RLE data. nAck I ...
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Register Definitions The register definitions are based on the standard IBM addresses for LPT. standard printer ports are supported. additional registers attach to an upper bit decode of the standard LPT port definition Table 39 - ECP Register Definitions NAME ...
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DATA and ecpAFifo PORT ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. WRITE operation, the ...
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Refer to the description of the interrupt under Operation, Interrupts. BIT 5 DIRECTION If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all other modes, Direction ...
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For example if 44h, 33h, 22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order as was written. cnfgA (Configuration Register A) ...
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BIT 1 full Read only 1: The FIFO cannot accept another byte or the FIFO is completely full. 0: The FIFO has at least 1 free byte. Table 41 - Extended Control Register R/W 000: Standard Parallel Port Mode . ...
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OPERATION Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ...
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Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features implemented by allowing the transfer of normal 8-bit data or 8-bit commands. When in the forward direction, normal data is transferred ...
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Interrupts The interrupts are enabled by serviceIntr in the ecr register. serviceIntr = 1 Disables the DMA and all of the service interrupts. serviceIntr = 0 Enables the selected interrupt condition. If the interrupting condition is valid, then the interrupt ...
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DMA TRANSFERS DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA services. ...
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PINTR pin. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode. Note: A threshold equivalent to a threshold of 15. These two cases are treated ...
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AUTO POWER MANAGEMENT Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the parallel port. logical device, two types of power management are provided; direct powerdown and auto powerdown. FDC Power Management ...
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Register Behavior Table 43 reiterates the AT and PS/2 (including Model 30) configuration registers available. It also shows the type of access permitted. order to maintain software transparency, access to all the registers must be maintained. As Table 43 shows, ...
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Table 43 - PC/AT and PS/2 Available Registers Base + Address Access to these registers DOES NOT wake up the part 00H 01H 02H 03H 04H 06H 07H 07H Access to these registers wakes up the part 04H 05H Note ...
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FDD Interface Pins All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either DISABLED or Table 45 - State of Floppy Disk Drive Interface Pins in Powerdown FDD Pins RDATA WP ...
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UART Power Management Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23- B4 and B5. When set, these bits allow the following auto power management operations: 1. The transmitter ...
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INTEGRATED DRIVE ELECTRONICS INTERFACE The FDC37C93x contains two IDE interfaces. This enables hard disks with embedded controllers (AT or IDE interfaced to the host processor. The IDE interface performs the address decoding for the IDE generates the buffer ...
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IDE OUTPUT ENABLES Two IDE output Enables are available. The IDE output enables treat all IDE transfers as 16 bit transfers. Option 1 Option 2 Note 1: The low and high byte transfer for IDE1 goes through external buffers controlled ...
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The FDC37C93x contains one 245 type buffer that can be used for a BIOS Buffer. If the BIOS buffer is not used, then nROMCS and nROMDIR must be tied high so as not to interfere with the boot ROM. nROMCS ...
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SD[15:8] FDC37C93x SD[7:0] IDE1_OE B1 IDE2_OE IDE Channel 1 BIOS NC IDE Channel 2 110 Option 2 ...
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GENERAL PURPOSE I/O FUNCTIONAL DESCRIPTION The FDC37C93x provides a set of flexible Input/Output control functions to the system designer through a set of General Purpose I/O pins (GPI/O). These GPI/O pins may perform simple I/O or may be individually configured ...
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Configuration Mode. The host uses an Index and Data register to access the GPI/O registers. The Power on default Index and Data registers are 0xEA ...
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The GPI/O port structure for each SD-bit D-TYPE nIOW 0 Transparent nIOR 1 GPI/O GPIO Register Configuration Bit-n Register bit-3 (Alt Function) Alternate Input Function GPI/O having an input-type alternate function. input pin buffer is ...
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Alternate Output Function SD-bit D-TYPE nIOW 0 Transparent 1 nIOR GPI/O Register Bit-n GPI/O having an output-type alternate function. [GP12--GP17, GP20, GP22--GP25] GPIO GPI/O Configuration Configuration Register bit-3 Register bit-1 (Alt Function) (Polarity GPI/O Configuration Register ...
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General Purpose I/O Configuration Registers Assigned to each GPI/O port is an 8-bit GPI/O Configuration Register which independently program each I/O port. GPI/O Configuration Registers accessible when the FDC37C93x is in the Configuration Mode; more information can be found in ...
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Table 48 - GPI/O Configuration Register Bits [3:0] ALT FUNC INT EN POLARITY BIT 3 BIT 2 BIT 1 0=DISABLE 0=DISABLE 0=NO INVERT 1=SELECT 1=ENABLE 1=INVERT ...
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Reading and Writing GPI/O Ports When a GPI/O port is programmed as an input, reading it through the GPI/O register latches either the inverted or non-inverted logic value present at the GPI/O pin; writing it has Table 49 - GPI/O ...
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Time-out status bit. The WDT interrupt is mapped to an interrupt channel through the WDT_CFG Configuration Register. mapped to an interrupt the interrupt request pin reflects the value of the WDT ...
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Table 51 - Watchdog Timer/Power LED Configuration Registers CONFIG REG. BIT FIELD WDT_VAL Bits[7:0] WDT_CFG Bit[0] Bit[1] Bit[2] Bit[3] Bits[7:4] WDT_CTRL Bit[0] Bit[1] Bit[2] Bit[3] Bits[7:4] General Purpose Address Decoder General Purpose I/O pin GP14 may be configured as a ...
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GP17 Joystick Function The FDC37C93x may be configured to generate a Joystick Write Strobe on GP17. When configured as a Joystick Write Strobe the output is a decode of the address = 0x201 qualified by IOW and AEN both active. ...
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Write EEPROM Data Register, 0xF3 Bits[7:0] This register allows the host to write data into the serial EEPROM. The FDC37C93x supports serial EEPROMS with x16 configurations. Two bytes must be written to this register in order to generate a EEPROM ...
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KEYBOARD CONTROLLER AND REAL TIME CLOCK FUNCTIONAL The FDC37C93x is a Super I/O, Real Time Clock and Universal Keyboard Controller that is designed for intelligent keyboard management in desktop computer applications. The Super I/O supports a Floppy Disk Controller, ...
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KEYBOARD AND RTC ISA INTERFACE The FDC37C93x ISA interface is functionally compatible with the 8042 style host interface. It consists of the D0-7 data bus; the nIOR, nIOW and the Status register, Table 52 - ISA I/O Address Map ( ...
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CPU-to-Host Communication The FDC37C93x CPU can write to the Output Table 53 - Host Interface Flags 8042 INSTRUCTION OUT DBB Set OBF, and, if enabled, the KIRQ output signal goes high Host-to-CPU Communication The host system can send both commands ...
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KEYBOARD POWER MANAGEMENT The keyboard provides support for two power- saving modes: soft powerdown mode and hard powerdown mode. In soft powerdown mode, the clock to the ALU is stopped but the timer/counter and interrupts are still ...
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This register is cleared on a reset. This register is read-only for the Host and read/write by the FDC37C93x CPU. UD Writable by FDC37C93x CPU. These bits are user-definable. C/D (Command Data)-This bit specifies whether the input data contains data ...
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REAL TIME CLOCK The Real Time Clock is a complete time of day clock with alarm and one hundred year calendar, a programmable periodic interrupt, and a programmable square wave generator. FEATURES Counts seconds, minutes, and hours of the day. ...
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RTC INTERRUPT The interrupt generated by the RTC is an active high output. The RTC interrupt output remains high as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. RESET_DRV or reading ...
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Time Calendar and Alarm The processor program obtains time and calendar information by reading the appropriate locations. The program may initialize the time, calendar and alarm by writing to these locations. The contents of the ten time, calendar and alarm ...
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Table 57 - Time, Calendar and Alarm Bytes ADD REGISTER FUNCTION 0 Register 0: Seconds 1 Register 1: Seconds Alarm 2 Register 2: Minutes 3 Register 3: Minutes Alarm 4 Register 4: Hours (12 hour mode) (24 hour mode) 5 ...
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Control and Status Registers The RTC has four registers REGISTER A (AH) MSB UIP DV2 DV1 UIP The update in progress bit is a status flag that may be monitored by the program. When UIP is a ...
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Table 59 - Divider Selection Bits OSCILLATOR REGISTER A BITS FREQUENCY DV2 DV1 32.768 KHz 0 0 32.768 KHz 0 0 32.768 KHz 0 1 32.768 KHz 0 1 32.768 KHz Table 60 - Periodic Interrupt ...
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REGISTER B (BH) MSB SET PIE AIE SET When the SET bit is a "0", the update functions normally by advancing the counts once per second. When the SET bit is a "1", an update cycle in ...
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REGISTER C (CH) - READ ONLY REGISTER MSB IRQF PF AF IRQF The interrupt request flag is set to a "1" when one or more of the following are true PIE = ...
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REGISTER D (DH) READ ONLY REGISTER MSB VRT 0 0 VRT When a "1", this bit indicates that the contents of the RTC are valid. A "0" appears in the VRT bit when the battery voltage is ...
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FREQUENCY DIVIDER The RTC has 22 binary divider stages following the clock input. The output of the divider signal to the update-cycle logic. The divider is controlled by the three divider bits (DV3-DV0) in Register A. ...
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The Configuration of the FDC37C93x is very flexible and is based on the configuration architecture implemented in typical Plug-and- Play components. The FDC37C93x is designed for motherboard applications in which the resources required by their components are known. With its ...
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Table 61 - Configuration Registers INDEX TYPE HARD RESET GLOBAL CONFIGURATION REGISTERS 0x02 W 0x00 0x03 R/W 0x03 0x07 R/W 0x00 0x20 R 0x02 0x21 R 0x01 0x22 R/W 0x00 0x23 R/W 0x00 0x24 R/W 0x04 0x2D R/W n/a 0x2E ...
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Table 61 - Configuration Registers INDEX TYPE HARD RESET 0x30 R/W 0x00 0x60, R/W 0x00, 0x61 0x00 0x62, R/W 0x00, 0x63 0x00 0x70 R/W 0x00 0xF0 R/W 0x00 LOGICAL DEVICE 3 CONFIGURATION REGISTERS (Parallel Port) 0x30 R/W 0x00 0x60, R/W ...
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Table 61 - Configuration Registers INDEX TYPE HARD RESET 0xF3 W n/a 0xF4 0x03 bits[6:0] R bit[7] R/W 0xF5 R n/a 0xF6 R n/a LOGICAL DEVICE 7 CONFIGURATION REGISTERS (Keyboard) 0x30 R/W 0x00 0x70 R/W 0x00 0x72 R/W 0x00 LOGICAL ...
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Table 61 - Configuration Registers INDEX TYPE HARD RESET 0xF3 R/W 0x00 Note1 0xF4 R/W 0x00 Note1 : this register contains some bits which are read or write only. SOFT RESET CONFIGURATION REGISTER n/a WDT_CFG n/a WDT_CTRL 141 ...
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Chip Level (Global) Control/Configuration Registers[0x00-0x2F] The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS Port for register selection. All unimplemented registers and bits ignore writes and return zero when ...
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Table 62 - Chip Level Registers REGISTER ADDRESS Device ID 0x20 R Hard wired = 0x02 Device Rev 0x21 R Hard wired = 0x01 PowerControl 0x22 R/W Default = 0x00. on POR or Reset_Drv hardware signal. Power Mgmt 0x23 R/W ...
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Table 62 - Chip Level Registers REGISTER ADDRESS Chip Level 0x25 -0x2C Reserved - Writes are ignored, reads return 0. Vendor Defined TEST 1 0x2E R/W TEST 2 0x2E R/W TEST 3 0x2F R/W Default = 0x00, on POR or ...
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Logical Device Configuration/Control Registers [0x30-0xFF] Used to access the registers that are assigned to each logical unit. This chip supports nine logical units and has nine sets of logical device registers. The nine logical devices are Floppy, IDE1, IDE2, Parallel, ...
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Table 63 - Logical Device Registers LOGICAL DEVICE REGISTER ADDRESS Interrupt Select (0x70,072) Defaults : 0x70 = 0x00, 0x72 = 0x00, (0x71,0x73) DMA Channel Select (0x74,0x75) Default = 0x04 32-Bit Memory Space (0x76-0xA8) Configuration Logical Device (0xA9-0xDF) Logical Device Config. ...
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Table 64 - I/O Base Address Configuration Register Description LOGICAL LOGICAL REGISTER DEVICE DEVICE INDEX NUMBER 0x00 FDC 0x60,0x61 0x01 IDE1 0x60,0x61 0x62,0x63 0x02 IDE2 0x60,0x61 0x62,0x63 BASE I/O RANGE (NOTE3) [0x100:0x0FF8 SRA +1 : SRB ON 8 ...
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Table 64 - I/O Base Address Configuration Register Description LOGICAL LOGICAL REGISTER DEVICE DEVICE INDEX NUMBER 0x03 Parallel 0x60,0x61 Port 0x04 Serial Port 0x60,0x61 1 0x05 Serial Port 0x60,0x61 2 0x06 RTC n/a 0x07 KYBD n/a 0x08 Aux. I/O 0x60,0x61 ...
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Table 65 - Interrupt Select Configuration Register Description NAME REG INDEX Interrupt 0x70 (R/W) Bits[3:0] selects which interrupt level is used for Interrupt 0. request level 0x00=no interrupt selected. select 0 0x01=IRQ1 0x02=IRQ2 0x0E=IRQ14 0x0F=IRQ15 Note: All interrupts are edge ...
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SMSC Defined Logical Device Configuration Registers The SMSC Specific Logical Device Table 67 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] NAME REG INDEX FDD Mode Register 0xF0 R/W Default = 0x0E FDD Option 0xF1 R/W ...
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Table 67 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] NAME REG INDEX FDD Type Register 0xF2 R/W Default = 0xFF 0xF3 R FDD0 0xF4 R/W Default = 0x00 FDD1 0xF5 R/W DEFINITION Bits[1:0] Floppy Drive ...
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Table 68 - IDE Drive 1, Logical Device 1 [Logical Device Number = 0x01] NAME REG INDEX IDE1 Mode Register Table 69 - IDE Drive 2, Logical Device 2 [Logical Device Number = 0x02] NAME REG INDEX IDE2 0xF0 R/W ...
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Table 70 - Parallel Port, Logical Device 3 [Logical Device Number = 0x03] NAME REG INDEX PP Mode Register 0xF0 R/W Default = 0x3C DEFINITION Bits[2:0] Parallel Port Mode = 100 Printer Mode (default) = 000 Standard and Bi-directional (SPP) ...
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Table 71 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04] NAME REG INDEX Serial Port 1 0xF0 R/W Mode Register Default = 0x00 Table 72 - Serial Port 2, Logical Device 5 [Logical Device Number = ...
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Table 73 - RTC, Logical Device 6 [Logical Device Number = 0x06] NAME REG INDEX RTC Mode Register 0xF0 R/W Default = 0x00 Serial EEPROM 0xF1 R/W Mode Register Default = 0x00 Serial EEPROM 0xF2 R/W Pointer Default = 0x00, ...
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Table 73 - RTC, Logical Device 6 [Logical Device Number = 0x06] NAME REG INDEX Write Status 0xF4 Default = 0x03, on Bit[6:0] POR, Reset_Drv Read Only or Software Reset. Bit[7] R/W DEFINITION Bits [1:0] = 1,1 Indicates that the ...
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Table 73 - RTC, Logical Device 6 [Logical Device Number = 0x06] Read EEPROM 0xF5 R Data Read Status 0xF6 R This register allows the host to read data from the serial EEPROM. Data is not valid in this register ...
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Table 74 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX GP10 0xE0 Default = 0x01 GP11 0xE1 Default = 0x01 GP12 0xE2 Default = 0x01 DEFINITION ...
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Table 74 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX GP13 0xE3 Default = 0x01 GP14 0xE4 Default = 0x01 GP15 0xE5 Default = 0x01 DEFINITION General Purpose I/0 bit 1.3 Bit[0] In/Out : ...
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Table 74 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX GP16 0xE6 Default = 0x01 GP17 0xE7 Default = 0x01 GP20 0xE8 Default = 0x01 DEFINITION General Purpose I/0 bit 1.6 Bit[0] In/Out : ...
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Table 74 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX GP21 0xE9 Default = 0x01 GP22 0xEA Default = 0x01 GP23 0xEB Default = 0x01 GP24 0xEC Default = 0x01 DEFINITION General Purpose I/0 ...
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Table 74 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX GP25 0xED Default = 0x01 0xEE-0xEF GP_INT 0xF0 Default = 0x00 GPA_GPW_EN 0xF1 Default = 0x00 WDT_VAL 0xF2 Default = 0x00 DEFINITION General Purpose ...
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Table 74 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX WDT_CFG 0xF3 Default = 0x00 DEFINITION Watch-dog timer Configuration Bit[0] Joy-stick Enable =1 WDT is reset upon an I/O read or write of the ...
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Table 74 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX WDT_CTRL 0xF4 Default = 0x00 Note: This register is also available at index 03 when not in configuration mode. See Table 47B. DEFINITION Watch-dog ...
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RESET_DRIVE This is an active high input. digitally filtered. When this input is detected the device powers its internal default state (all logical devices disabled) and remains inactive until configured otherwise. Sequence of Operation 1. At power-up, or ...
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FDC Core Modifications 1. FDC DMA Mode to default to Non-Burst Mode. a. Register xx Bit x is default powerup. 2. FDC Core command to handle Density Select function. Implement to simplify support of 3-Mode drives ...
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DT0 DT1 DRVDEN0 ( DENSEL 0 1 DRATE1 1 0 nDENSEL 1 1 DRATE0 There are two of the following registers in the configuration data space, one for each drive. FDD0 - 0xF4 FDD1 - 0xF5 D7 D6 ...
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Logical Device IRQ and DMA Operation 1. IRQ and DMA Enable and Disable: Any time the IRQ or DACK for a logical block is disabled by a register bit in that logical block, the IRQ and/or DACK must be disabled. ...
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The ECP Parallel port Config Reg B reflects the IRQ and DRQ selected by the Configuration Registers. Table "A" CONFIG REG B IRQ SELECTED BITS 5:3 15 110 14 101 11 100 10 011 9 010 7 001 5 ...
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OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range......................................................................................... 0 Storage Temperature Range..........................................................................................-55 Lead Temperature Range (soldering, 10 seconds) .................................................................... +325 Positive Voltage on any pin, with respect to Ground ................................................................V Negative Voltage on any pin, with respect to Ground.................................................................... -0.3V ...
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PARAMETER SYMBOL Input Leakage (All I and IS buffers) Low Input Leakage High Input Leakage V BAT Standby Current I BAT Input Leakage O4 Type Buffer Low Output Level V High Output Level Output Leakage O8SR Type Buffer Low Output ...
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PARAMETER SYMBOL O16SR Type Buffer Low Output Level V High Output Level Output Leakage Rise Time Fall Time OD16P Type Buffer Low Output Level Output Leakage OD24 Type Buffer Low Output Level Output Leakage OD48 Type Buffer Low Output Level ...
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PARAMETER SYMBOL OCLK2 Type Buffer Low Output Level High Output Level Output Leakage ChiProtect (SLCT, PE, BUSY, nACK, nERROR) Backdrive (nSTROBE, nAUTOFD, nINIT, nSLCTIN) Backdrive (PD0-PD7) Suppy Current Active Note 1: All output leakages are measured with the current pins ...
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Vcc Reg 71 FIGURE 3 - POWER-UP TIMING NAME DESCRIPTION t1 Vcc Slew from 4. Vcc Slew from 0V to 4.5V t3 Reg 71 after powerup (Note 1) Note 1: Internal write-protection period after Vcc passes ...
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AEN t3 SA[x], nCS t1 nIOW SD[x] GP I/O FINTR PINTR IBF NAME DESCRIPTION t1 SA[x], nCS and AEN valid to nIOW asserted t2 nIOW asserted to nIOW deasserted t3 nIOW asserted to SA[x], nCS invalid t4 SD[x] Valid to ...
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AEN SA[x], nCS t1 nIOR SD[x] PD[x], nERROR, PE, SLCT, ACK, BUSY FINTER PINTER PCOBF AUXOBF1 nIOR/nIOW SEE TIMING PARAMETERS ON PAGE 177 DATA VALID t9 t8 FIGURE 5A - ISA READ 176 t13 t6 t5 ...
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FIGURE 5B - ISA READ TIMING NAME DESCRIPTION t1 SA[x], nCS and AEN valid to nIOR asserted t2 nIOR asserted to nIOR deasserted t3 nIOR asserted to SA[x], nCS invalid t4 nIOR asserted to Data Valid t5 Data Hold/float from ...
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PCOBF AUXOBF1 nWRT IBF nRD FIGURE 6 - INTERNAL 8042 CPU TIMING NAME DESCRIPTION t1 nWRT deasserted to AUXOBF1 asserted (Notes 1,2) t2 nWRT deasserted to PCOBF asserted (Notes 1,3) t3 nRD deasserted to IBF deasserted (Note 1) Note 1: ...
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FIGURE 7A - INPUT CLOCK TIMING NAME DESCRIPTION t1 Clock Cycle Time for 14.318MHZ t2 Clock High Time/Low Time for 14.318MHz t1 Clock Cycle Time for 32KHZ t2 Clock High Time/Low Time for 32KHz Clock Rise Time/Fall ...
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IDEx_IRQ IRQx NAME DESCRIPTION t1 IDE_IRQ low-high edge to IRQ low-high edge propagation delay. Edge High type interrupt selected. t2 IDE_IRQ high-low edge to IRQ high-low edge propagation delay. Edge high type interrupt selected. Note: IDE IRQ input and pass-through ...
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SDx t1 A[x] nIOR nIOROP nIOW nIOWOP FIGURE 9 - SA[x], nIOROP, nIOWOP TIMING NAME DESCRIPTION t1 SD[ A[x] output t2 nIOR in to nIOROP output t3 nIOW in to nIOWOP output MIN ...
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RD[x] Note 1 SD[x] FIGURE 10 - ROM INTERFACE TIMING Note 1: RD[x] driven by FDC37C93x, SD[x] driven by system Note 2: RD[x] driven by ROM, SD[x] driven by FDC37C9x NAME DESCRIPTION t1 SD[x] valid to ...
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AEN FDRQ, PDRQ t1 nDACK t14 nIOR or nIOW DATA (DO-D7) TC FIGURE 11 - DMA TIMING NAME DESCRIPTION t1 nDACK Delay Time from FDRQ High t2 DRQ Reset Delay from nIOR or nIOW t3 FDRQ Reset Delay from nDACK ...
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nDS0-3 nINDEX nRDATA nWDATA nIOW t9 nDS0-3, MTR0-3 FIGURE 12 - DISK DRIVE TIMING (AT MODE ONLY) NAME DESCRIPTION t1 nDIR Set Up to STEP Low t2 nSTEP Active Time Low t3 nDIR ...
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IRQx nCTSx, nDSRx, nDCDx t2 IRQx nIOW IRQx nIOR nRIx FIGURE 13 - SERIAL PORT TIMING NAME DESCRIPTION t1 nRTSx, nDTRx Delay from nIOW t2 IRQx Active Delay from nCTSx, nDSRx, nDCDx t3 IRQx Inactive Delay from ...
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A0-A9 t2 nIDEENLO, t1 nIDEENHI, nHDCSx, nGAMECS FIGURE 14 - IDE INTERFACE TIMING NAME DESCRIPTION t1 nIDEENLO, nIDEENHI, nGAMECS, nHDCSx Delay from nAEN t2 nIDEENLO, nIDEENHI, nGAMECS, nHDCSx Delay from nIDEENLO Delay from nIDEENHI, AEN ...
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PD0- PD7 nIOW nINIT, nSTROBE. nAUTOFD, SLCTIN nACK nPINTR (SPP) PINTR (ECP or EPP Enabled) nFAULT (ECP) nERROR (ECP) PINTR FIGURE 15 - PARALLEL PORT TIMING NAME DESCRIPTION t1 PD0-7, nINIT, nSTROBE, nAUTOFD Delay from nIOW t2 PINTR Delay from ...
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A0-A10 SD<7:0> t17 t8 nIOW t10 IOCHRDY t13 t22 t20 nWRITE t1 PD<7:0> t16 t3 t14 nDATAST nADDRSTB nWAIT t21 PDIR FIGURE 16A - EPP 1.9 DATA OR ADDRESS WRITE CYCLE SEE TIMING PARAMETERS ON PAGE 189 t18 t9 t12 ...
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FIGURE 16B - EPP 1.9 DATA OR ADDRESS WRITE CYCLE TIMING NAME DESCRIPTION t1 nIOW Asserted to PDATA Valid t2 nWAIT Asserted to nWRITE Change (Note 1) t3 nWRITE to Command Asserted t4 nWAIT Deasserted to Command Deasserted (Note 1) ...
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A0-A10 t19 IOR SD<7:0> t8 IOCHRDY t24 t23 PDIR t9 t21 nWRITE t2 t25 PD<7:0> t28 t26 t1 t14 DATASTB ADDRSTB nWAIT FIGURE 17A - EPP 1.9 DATA OR ADDRESS READ CYCLE SEE TIMING PARAMETERS ON PAGE 191 t20 t11 ...
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FIGURE 17B - EPP 1.9 DATA OR ADDRESS READ CYCLE TIMING PARAMETERS NAME DESCRIPTION t1 PDATA Hi-Z to Command Asserted t2 nIOR Asserted to PDATA Hi-Z t3 nWAIT Deasserted to Command Deasserted (Note 1) t4 Command Deasserted to PDATA Hi-Z ...
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A0-A10 SD<7:0> t17 t8 nIOW t10 t20 IOCHRDY t13 nWRITE t1 PD<7:0> nDATAST nADDRSTB nWAIT PDIR FIGURE 18A - EPP 1.7 DATA OR ADDRESS WRITE CYCLE SEE TIMING PARAMETERS ON PAGE 193 t6 t12 t11 t16 t3 192 t18 t9 ...
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FIGURE 18B - EPP 1.7 DATA OR ADDRESS WRITE CYCLE PARAMETERS NAME DESCRIPTION t1 nIOW Asserted to PDATA Valid t2 Command Deasserted to nWRITE Change t3 nWRITE to Command t4 nIOW Deasserted to Command Deasserted (Note 2) t5 Command Deasserted ...
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A0-A10 t19 nIOR SD<7:0> IOCHRDY nWRITE PD<7:0> t23 nDATASTB nADDRSTB nWAIT PDIR FIGURE 19A - EPP 1.7 DATA OR ADDRESS READ CYCLE SEE TIMING PARAMETERS ON PAGE 195 t20 t15 t11 t13 t12 t10 t5 t2 194 t22 ...
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FIGURE 19B - EPP 1.7 DATA OR ADDRESS READ CYCLE PARAMETERS NAME DESCRIPTION t2 nIOR Deasserted to Command Deasserted t3 nWAIT Asserted to IOCHRDY Deasserted t4 Command Deasserted to PDATA Hi-Z t5 Command Asserted to PDATA Valid t8 nIOR Asserted ...
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ECP PARALLEL PORT TIMING Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500Kbytes/sec allowed in the forward direction using DMA. The state machine does not examine and begins the next transfer based ...
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Microsoft. The dynamic driver PDATA nSTROBE BUSY FIGURE 20 - PARALLEL PORT FIFO TIMING NAME DESCRIPTION t1 DATA Valid to nSTROBE Active t2 nSTROBE Active Pulse Width t3 DATA Hold from nSTROBE Inactive (Note 1) t4 nSTROBE Active ...
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PDATA<7:0> nACK t4 nAUTOFD FIGURE 21 - ECP PARALLEL PORT REVERSE TIMING NAME DESCRIPTION t1 nAUTOFD Valid to nSTROBE Asserted t2 PDATA Valid to nSTROBE Asserted t3 BUSY Deasserted to nAUTOFD Changed (Notes 1,2) t4 BUSY Deasserted to PDATA Changed ...
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PDATA<7:0> t6 BUSY FIGURE 22 - ECP PARALLEL PORT FORWARD TIMING NAME DESCRIPTION t1 PDATA Valid to nACK Asserted t2 nAUTOFD Deasserted to PDATA Changed t3 nACK Asserted to nAUTOFD Deasserted (Notes 1,2) t4 nACK Deasserted to nAUTOFD Asserted ...
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DETAIL "A" 120 R1 R2 121 D1/4 160 0.10 A1 -C- MIN NOM MAX A 4.07 A1 0.05 0.5 A2 3.10 3.67 D 30.95 31.20 31.45 D1 27.90 28.00 ...