FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 117

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Reading and Writing GPI/O Ports
When a GPI/O port is programmed as an input,
reading it through the GPI/O register latches
either the inverted or non-inverted logic value
present at the GPI/O pin;
WATCH DOG TIMER/POWER LED CONTROL
Basic Functions
The FDC37C93x contains a Watch Dog Timer
(WDT) and also has the capability to directly
drive the system's Power-on LED.
The
(WDT_CTRL bit-0) is mapped to GP12 when
the
Configuration Register is set "and" bit-6 of the
IR Options Register = 0. In addition, the Watch
Dog Time-out status bit may be mapped to an
interrupt through the WDT_CFG Configuration
Register.
GP13 may be configured as a high current LED
driver to drive the Power LED.
accomplished by setting the alternate function
bit of the GP13 Configuration Register "and"
clearing bit-6 of the IR Options Register.
The Infared signals, IRRX and IRTX, are
mapped to GP12 and GP13 when the alternate
function
Configuration Registers is set "and" bit-6 of the
IR Options Register is set.
Read
Write
alternate
HOST OPERATION
Watch
bit
of
Dog
function
the
Time-out
GP12
bit
Table 49 - GPI/O Read/Write Behavior
of
writing it has
latched value of GPI/O pin
no effect
and
status
the
GPI/O INPUT PORT
This is
GP12
GP13
bit
117
as an output, the logic value written into the
GPI/O register is either output to or inverted to
the GPI/O pin; when read the result will reflect
the contents of the GPI/O register bit. This is
sumarized in Table 49.
Watch Dog Timer
The FDC37C93x's WDT has a programmable
time-out ranging from 1 to 255 minutes with one
minute resolution. The WDT time-out value is
set
register. Setting the WDT_VAL register to 0x00
disables the WDT function (this is its power on
default).
non-zero value will cause the WDT to reload
and begin counting down from the value loaded.
counter stops and sets the Watchdog time-out
status bit in the WDT_CTRL Configuration
Register. Note: Regardless of the current state
of the WDT, the WDT time-out status bit can be
directly set or cleared by the Host CPU.
There are three system events which can reset
the WDT, these are a Keyboard Interrupt, a
Mouse Interrupt, or I/O reads/writes to address
0x201 (the internal or an external Joystick Port).
events may be individually enabled or disabled
through bits in the WDT_CFG configuration
register.
through the WDT_CFG register, the occurence
of that event will cause the WDT to reload the
value stored in WDT_VAL and reset the WDT
time-out status bit if set.
events are disabled the WDT will inevitably time
out.
When the WDT count value reaches zero the
The effect on the WDT for each of these system
through
Setting the WDT_VAL to any other
When a system event is enabled
bit value in GP register
bit placed in GP register
the
GPI/O OUTPUT PORT
WDT_VAL
If all three system
Configuration