FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 135

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

REGISTER D (DH) READ ONLY REGISTER
VRT
When a "1", this bit indicates that the contents
of the RTC are valid. A "0" appears in the VRT
bit when the battery voltage is low. The VRT bit
is read only bit which can only be set by a read
of Register D. Refer to Power Management for
the conditions when this bit is reset.
processor program can set the VRT bit when the
time and calendar are initialized to indicate that
the time is valid.
b6:b0
The remaining bits of Register D are read as
zeros and cannot be written.
Register EH-FFH: General purpose
Registers Eh-FFH are general purpose CMOS
registers. These registers can be used by the
host or 8051 and are fully available during the
time update cycle.
registers are preserved by the battery power.
INTERRUPTS
The RTC includes three separate fully automatic
sources of interrupts to the processor.
alarm interrupt may be programmed to occur at
rates from one-per-second to one-a-day. The
periodic interrupt
from half-a-second to 122.070 us. The update
ended interrupt may be used to indicate to the
program that an update cycle is completed.
Each
described in greater detail in other sections.
MSB
VRT
b7
of
these independent interrupts
b6
0
may be selected for rates
The contents of these
b5
0
b4
0
The
The
are
135
The processor program selects which interrupts,
if any, it wishes to receive by writing a "1" to
the appropriate enable bits in Register B. A "0"
being asserted due to that interrupt cause.
When an interrupt event occurs a flag bit is set
to a "1" in Register C. Each of the three interrupt
sources have separate flag bits in Register C,
which are set independent of the state of the
corresponding enable bits in Register B. The
flag bits may be used with or without enabling
the corresponding enable bits. The flag bits in
Register C are cleared (record of the interrupt
event is erased)
Double
ensure the bits
throughout the read cycle. All bits which are
high when read by the program are cleared,
and new interrupts are held until after the read
cycle. If an interrupt flag is already set when
the interrupt becomes enabled, the IRQB port is
immediately activated, though the interrupt
initiating the event may have occurred much
earlier.
When an interrupt flag bit is set and the
corresponding interrupt-enable bit is also set,
the IRQB port is driven low. IRQB is asserted as
long as at least one of the three interrupt
sources has its flag and enable bits both set.
The IRQF bit in Register C is a "1" whenever the
IRQB port is being driven low.
in an enable bit prohibits the IRQB port from
b3
0
latching is included in Register C to
b2
0
when Register C is read.
that are
b1
0
set are stable
LSB
b0
0