FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 152

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

16 Bit Address Qualification
When IDE2 is not active (IDE2 active bit = L2 - CR30 - Bit0), nHDCS2, nHDCS3 and IDE2_IRQ are in
high impedance; 16_ADR = CR24.6.
IDE1
Mode Register
IDE2
Mode Register
Default = 0x00
IDE2_IRQ (pin 29)
nHDCS2 (pin 27)
nHDCS3 (pin 28)
nCS (pin 53)
NAME
NAME
Table 68 - IDE Drive 1, Logical Device 1 [Logical Device Number = 0x01]
Table 69 - IDE Drive 2, Logical Device 2 [Logical Device Number = 0x02]
REG INDEX
REG INDEX
0xF0 R/W
IDE2 ACTIVE BIT = 1
16BIT_ADR = X
Input (SA12)
Input (IRQ)
Output
Output
IDE1 HI and LO byte pass through external buffers
controlled by IDE1_OE.
Bit[0] : IDE2 Configuration Options
Bits[7:1] : Reserved, set to zero
= 0 :
= 1 :
IDE2 HI and LO bytes pass through external
buffers controlled by IDE2_OE.
IDE2_OE not used. IDE2 HI and LO byte
passes through external buffer controlled by
IDE1_OE.
152
IDE2 ACTIVE BIT = 0
16BIT_ADR = 0
Input (SA12)
DEFINITION
DEFINITION
Hi-Z
Hi-Z
Hi-Z
IDE2 ACTIVE BIT = 0
16BIT_ADR = 1
Input (SA13)
Input (SA14)
Input (SA15)
Input (SA12)
STATE
STATE
C