FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 112

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

by the host when the chip is in the normal run
mode, i.e., not in Configuration Mode. The host
uses an Index and Data register to access the
GPI/O registers. The Power on default Index
and Data registers are 0xEA and 0xEB
respectively. When the chip is in configuration
mode these Index and Data registers are used
to access the internal configuration registers. In
configuration mode the Index address may be
programmed to reside on addresses 0xE0,
0xE2, 0xE4 or 0xEA.
automatically set to the Index address + 1.
Upon exiting the configuration mode the new
Note 1: Watchdog timer control register L8 - F4 is also available at index 03 when not in
configuration mode.
REGISTER
Index
Data
INDEX
Table 47B - Index and Data Register Normal (Run) Mode
0x01
0x02
0x03
The Data address is
OxE0, E2, E4, EA
Index address + 1
Table 47A - Index and Data Register
ADDRESS
Access to Watchdog Timer Control (L8 - CRF4)
NORMAL (RUN) MODE
112
Watchdog Timer Control
NORMAL (RUN) MODE
Access to GP1
Access to GP2
Access to GP1, GP2,
registers GP1 and GP2.
To access the GP1 register the host should first
Index register (at 0xEX) to select GP1 and then
read or write the Data register (at Index+1) to
access the GP1 register. To access GP2 the
host should perform an IOW of 0x02 to the
Index register and then access GP2 through the
Data register. Additionally the host can access
the WDT_CTRL (Watch Dog Timer Control)
Configuration Register while in the normal (run)
mode by writing an 0x03 to the index register.
make sure the chip is in the normal (run) mode.
Then it should perform an IOW of 0x01 to the
(see Table 47B)
0x01-0x03
CONFIG MODE
Configuration
0x00-0xFF
Access to
Registers
Internal