FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 120

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

GP17 Joystick Function
The FDC37C93x may be configured to generate
a Joystick Write Strobe on GP17. When
configured as a Joystick Write Strobe the output
is a decode of the address = 0x201 qualified by
IOW and AEN both active.
The Joystick Write Strobe is normally active
low,
through a bit in the GP20 configuration register.
IDE2 Buffer Enable/Reset Out
The FDC37C93x may be configured to provide
an nIDE2_OE buffer enable signal on pin GP20.
The IDE2 Mode Register (0xF0 of Logical
Device 2) contains a bit which determines
whether nIDE1_OE or nIDE2_OE is active for
IDE2 transfers.
General Purpose I/O pin, IDE2 I/O accesses
must be configured to activate nIDE1_OE for
IDE2 transfers if a secondary Hard Drive
interface is present. The polarity of nIDE2_OE,
which is normally active low, is programmable
through a bit in the GP20 configuration register.
Serial EEPROM Interface
Four of the FDC37C93x's general purpose I/O
pins may be configured to provide a 4 wire
direct interface to a family of industry standard
serial EEPROMs.
polarity bits of these four pins must be set to 0
(non-inverting). The interface is depicted below
and will allow connection to either a 93C06
(256-bit), a 93C46 (1K-bit), a 93C56 (2K-bit), or
a 93C66 (4K-bit) device.
GP21 <---- Serial EEPROM Data In
GP22 ----> Serial EEPROM Data Out
GP23 ----> Serial EEPROM Clock
GP24 ----> Serial EEPROM Enable
however its polarity is programmable
If GP20 is selected as a
For proper operation the
120
keyboard controller (Port 20). The FDC37C93x
may be configured to drive this signal onto
GP20 by programming its GP I/O configuration
register. Access to the serial EEPROM is only
available when the FDC37C93x is in the
configuration mode. A set of six configuration
registers, located in Logical Device 6 (RTC) is
used to fully access and configure the serial
EEPROM. The registers are defined as follows:
Serial EEPROM Mode Register, 0xF1
Bits[3:0]
These are the lock bits which once set deny
access to the serial EEPROM's first 128 bytes in
32 byte blocks. Bit 0 locks the first block, bit 1
the second block, bit 2 the third block and bit 3
the fourth block of 32 bytes. Once these lock
bits are set they cannot be reset in any way
other than by a Hard reset or a Power-on reset.
Bit[4]
This selects the type of EEPROM connected to
the FDC37C93x. If cleared the device must be
either a 93C06 or 93C46 and if set the device
must be either an 93C56 or 93C66.This bit must
be properly set before attempting to access the
serial EEPROM.
Bits[7:5]
Reserved, set to zero.
Serial EEPROM Pointer Register, 0xF2
Bits[7:0]
Use this register to set the Serial EEPROM's
pointer.
reflects the current EEPROM pointer address.
The Serial Device Pointer increments after each
pair of reads from the Resource Data register or
after each pair of writes to the Program
Resource Data register.
The value in this register always