FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 126

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

This register is cleared on a reset. This register
is read-only for the Host and read/write by the
FDC37C93x CPU.
UD
C/D
IBF
OBF
is
Writable by FDC37C93x CPU.
These bits are user-definable.
(Command Data)-This bit specifies
whether
contains data or a command (0 =
data, 1 = command). During a host
data/command write operation, this
bit is set to "1" if SA2 = 1 or reset to
"0" if SA2 = 0.
(Input Buffer Full)- This flag is set to
1 whenever the host system writes
data into the input data register.
Setting this flag activates the
FDC37C93x CPU's nIBF (MIRQ)
interrupt if enabled. When the
FDC37C93x CPU reads the input
data register (DBB), this bit is
automatically reset and the interrupt
is cleared. There is no output pin
associated with this internal signal.
KCLK
KDAT
MCLK
MDAT
Host I/F Data Reg
Host I/F Status Reg
RTCCNTRL
RTCADDR
RTCDATA
(Output Buffer Full)- This flag
NC: No Change N/A: Not Applicable
the
DESCRIPTION
input
data
register
Table 55 - Resets
set
126
HARDWARE RESET (RESET)
EXTERNAL CLOCK SIGNAL
The FDC37C93x X1K clock source is a 12 MHz
clock generated from a 14.318 MHz clock. The
reset pulse must last for at least 24 16 Mhz
clock periods.
applies
generated reset signals. In powerdown mode,
the external clock signal on X1K is not loaded by
the chip.
The FDC37C93x X1C clock source must be
from a crystal connected across X1C and X2C.
Due to the low current internal oscillator circuit,
this X1C can not be driven by an external clock
signal.
DEFAULT RESET CONDITIONS
The FDC37C93x has one source of reset: an
external reset via the RESET pin.
Table 55 for the effect of each type of reset on
the internal registers.
write to the output data register (DBB).
When the host system reads the output
data register, this bit is automatically reset.
to
Weak High
Weak High
Weak High
Weak High
00H
80H
N/A
NC
NC
both
The pulse-width requirement
internally
and
externally
Refer to