FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 198

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Note 1: Maximum value only applies if there is data in the FIFO waiting to be written out.
Note 2: BUSY is not considered asserted or deasserted until it is stable for a minimum of 75 to 130
PDATA<7:0>
NAME
nAUTOFD
t1
t2
t3
t4
t5
t6
t7
t8
nACK
ns.
nAUTOFD Valid to nSTROBE Asserted
PDATA Valid to nSTROBE Asserted
BUSY Deasserted to nAUTOFD Changed
(Notes 1,2)
BUSY Deasserted to PDATA Changed (Notes 1,2)
nSTROBE Deasserted to Busy Asserted
nSTROBE Deasserted to Busy Deasserted
BUSY Deasserted to nSTROBE Asserted (Notes 1,2)
BUSY Asserted to nSTROBE Deasserted (Note 2)
FIGURE 21 - ECP PARALLEL PORT REVERSE TIMING
t4
DESCRIPTION
t1
t5
t3
198
t6
t4
MIN
80
80
80
80
0
0
0
0
TYP
t2
MAX
180
180
200
180
60
60
UNITS
ns
ns
ns
ns
ns
ns
ns
ns