FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 131

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Control and Status Registers
The
REGISTER A (AH)
UIP
The update in progress bit is a status flag that
may be monitored by the program. When UIP is
a "1" the update cycle is in progress or will soon
begin. When UIP is a "0" the update cycle is not
in progress and will not be for at least 244us.
The time, calendar, and alarm information is
fully available to the program when the UIP bit is
zero. The UIP bit is a read only bit and is not
affected by RESET_DRV. Writing the SET bit in
Register B to a "1" inhibits any update cycle and
then clears the UIP status bit. The UIP bit is only
valid when the RTC is enabled. Refer to Table
58.
DV2-0
Three bits are used to permit the program to
select various conditions of the 22 stage divider
chain.
combinations. The divider selection bits are
MSB
UIP
b7
RTC
Table
has
DV2
b6
59
four
shows
registers
DV1
b5
the
which
allowable
DV0
b4
are
131
times, even during the update cycle.
also used to reset the divider chain. When the
time/calendar is first initialized, the program
may start the divider chain at the precise time
stored in the registers. When the divider reset is
removed the first update begins one-half second
later. These three read/write bits are not affected
by RESET_DRV.
RS3-0
The four rate selection bits select one of 15 taps
on the divider chain or disable the divider
output. The selected tap determines rate or
frequency of the periodic interrupt. The program
may enable or disable the interrupt with the PIE
bit in Register B. Table 60 lists the periodic
interrupt rates and equivalent output frequencies
that may be chosen with the RS0 - RS3 bits.
These four bits are read/write bits which are not
affected by RESET_DRV.
RS3
b3
RS2
b2
RS1
b1
RS0
LSB
b0