FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 39

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

SK
SRT
ST0
ST1
ST2
ST3
WGATE
SYMBOL
Skip Flag
Step Rate Interval The time interval between step pulses issued by the FDC.
Status 0
Status 1
Status 2
Status 3
Write Gate
NAME
Table 19 - Description of Command Symbols
Verify command when EC is set.
When set to 1, sectors containing a deleted data address mark will
automatically be skipped during the execution of Read Data. If
Read Deleted is executed, only sectors with a deleted address
mark will be accessed. When set to "0", the sector is read or
written the same as the read and write commands.
Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms
at the 1 Mbit data rate. Refer to the SPECIFY command for actual
delays.
Registers within the FDC which store status information after a
command has been executed. This status information is available
to the host during the result phase after command execution.
Alters timing of WE to allow for pre-erase loads in perpendicular
drives.
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DESCRIPTION