FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 143

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Device ID
Hard wired
= 0x02
Device Rev
Hard wired
= 0x01
PowerControl
Default = 0x00.
on POR or
Reset_Drv hardware
signal.
Power Mgmt
Default = 0x00.
on POR or
Reset_Drv hardware
signal
OSC
Default = 0x04, on
POR or Reset_Drv
hardware signal.
REGISTER
ADDRESS
0x22 R/W
0x23 R/W
0x24 R/W
0x20 R
0x21 R
Table 62 - Chip Level Registers
Chip Level, SMSC Defined
A read only register which provides device
identification. Bits[7:0] = 0x02 when read
A read only register which provides device revision
information. Bits[7:0] = 0x01 when read
Bit[0] FDC Power
Bit[1] IDE1 Enable
Bit[2] IDE2 Enable
Bit[3] Parallel Port Power
Bit[4] Serial Port 1 Power
Bit[5] Serial Port 2 Power
Bit[6:7] Reserved (read as 0)
= 0 Power off or disabled
= 1
Bit[0] FDC
Bit[1] IDE1
Bit[2] IDE2
Bit[3] Parallel Port
Bit[4] Serial Port 1
Bit[5] Serial Port 2
Bit[6:7] Reserved (read as 0)
= 0 Intelligent Pwr Mgmt off
= 1
Bits[1:0] Reserved, set to zero
Bits[3:2] OSC
= 01
= 10
= 00
= 11
Bit [5:4] Reserved, set to zero
Bit [6] 16 Bit Address Qualification
= 0 12 Bit Address Qualification
= 1 16 Bit Address Qualification
Bit[7] IRQ8 Polarity
(Refer to the 16-bit Address Qualification in the
SMSC Defined Logical Device Configuration
Register, Device 2 section.)
Power on or enabled
Intelligent Pwr Mgmt on
Osc is on, BRG clock is on.
Same as above (01) case.
Osc is on, BRG Clock Enabled.
Osc is off, BRG clock is disabled.
143
DESCRIPTION
STATE
C
C
C
C
C