FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 168

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Logical Device IRQ and DMA Operation
1.
IRQ and DMA Enable and Disable: Any time the IRQ or DACK for a logical block is disabled by a
register bit in that logical block, the IRQ and/or DACK must be disabled. This is in addition to the
IRQ and DACK disabled by the Configuration Registers (active bit or address not valid).
a.
b.
c.
d.
e.
f.
g.
(FROM ECR REGISTER)
FDC: For the following cases, the IRQ and DACK used by the FDC are disabled
(high
i.
ii.
IDE1 and IDE2: No additional conditions.
Serial Port1 and 2:
i.
Parallel Port:
i.
ii.
Game Port and ADDR: No IRQ or DACK used.
Real Time Clock (RTC):
i.
Keyboard Controller (KYBD):
000
001
010
011
100
101
110
111
Digital Output Register (Base+2) bit D3 (DMAEN) set to "0".
The FDC is in power down (disabled).
Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic "0", the
serial port interrupt is forced to a high impedance state - disabled.
SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to "0", IRQ is
disabled (high impedance).
ECP Mode:
(refer to the RTC section of this data sheet.)
MODE
impedance). Will not respond to the DREQ
(1)
(2)
PRINTER
CONFIG
(DMA) dmaEn from ecr register. See table.
IRQ - See table.
TEST
FIFO
ECP
RES
SPP
EPP
168
CONTROLLED BY
IRQ PIN
IRQE
IRQE
IRQE
IRQE
IRQE
(on)
(on)
(on)
CONTROLLED BY
PDREQ PIN
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn