FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 142

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Chip Level (Global) Control/Configuration
Registers[0x00-0x2F]
The chip-level (global) registers lie in the
address range [0x00-0x2F]. The design MUST
use all 8 bits of the ADDRESS Port for register
selection. All unimplemented registers and bits
ignore writes and return zero when read.
Config Control
Default = 0x00
Index Address
Logical Device #
Default = 0x00
Card Level
Reserved
REGISTER
0x08 - 0x1F Reserved - Writes are ignored, reads return 0.
0x04 - 0x06 Reserved - Writes are ignored, reads return 0.
ADDRESS
0x03 R/W
0x07 R/W
0x02 W
0x00 -
0x01
Chip (Global) Control Registers
Table 62 - Chip Level Registers
Reserved - Writes are ignored, reads return 0.
The hardware automatically clears this bit after the
write, there is no need for software to clear the bits.
Bit 0 = 1: Soft Reset. Refer to the "Configuration
Registers" table for the soft reset value for each
register.
Bit[7]
= 1 Enable GP1, GP2, +WDT_CTRL when not in
= 0 Disable GP1, GP2, +WDT_CTRL access
Bits [6:2]
Reserved - Writes are ignored, reads return 0.
Bits[1:0]
Sets GP1/GP2 selection register used when in Run
mode (not in Configuration Mode).
= 11
= 10
= 01
= 00
A write to this register selects the current logical
device.
configuration registers for each logical device.
Note: the Activate command operates only on the
selected logical device.
configuration mode
when not in configuration mode (Default)
0xEA (Default)
0xE4
0xE2
0xE0
This allows access to the control and
142
configuration register in the chip.
PORT
register. These registers are accessable only in
the Configuration Mode.
DESCRIPTION
is then used to access the selected
The DATA
STATE
C
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