SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 55

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

Philips Semiconductors
Figure 2-3. ICP - Windows on the PC screen and data structures in SDRAM for two live video windows.
window on the PC video screen while the PC is running
a graphical user interface. The first step (if necessary)
would use the ICP in memory-to-memory mode to per-
form a vertical resizing. The second step would use the
ICP in memory-to-PCI mode to perform horizontal resiz-
ing and optional colorspace conversion from YUV to
RGB.
While sending the final, resampled and converted pixels
over the PCI bus to the video frame buffer, the ICP uses
a full, per-pixel occlusion bit mask—accessed in destina-
tion coordinates—to determine which pixels are actually
written to the graphics card frame buffer for display. Con-
ditioning the transfer with the bit mask allows PNX1300
to accommodate an arbitrary arrangement of overlap-
ping windows on the PC video screen.
Figure 2-3
data structures in SDRAM that support ICP operation.
On the left, the PC video screen has four overlapping
windows. Two, Image 1 and Image 2, are being used to
display video generated by PNX1300. The right side
shows a conceptual view of SDRAM contents. Two data
structures are present, one for Image 1 and the other for
Image 2.
which the ICP is displaying Image 2.
When the ICP is displaying an image (i.e., copying it from
SDRAM to a frame buffer), it maintains four pointers to
the SDRAM data structures. Three pointers locate the Y,
U, and V data arrays, the fourth locates the per-pixel oc-
clusion bit map. The Y, U, and V arrays are indexed by
source coordinates while the occlusion bit map is ac-
cessed with screen coordinates.
As the ICP generates pixels for display, it performs hori-
zontal scaling and colorspace conversion. The final RGB
PC Screen
Figure 2-3
Image 1
illustrates a possible display situation and the
File
FrameMaker 5
Edit
represents a point in time during
Format View
IMAGE 1
File
Calendar
Edit
Image 2
ICP
pixel value is then copied to the destination address in
the screen’s frame buffer only if the corresponding bit in
the occlusion bit map is a ‘1’.
As shown in the conceptual diagram, the occlusion bit
map has a pattern of 1s and 0s corresponding to the
shape of the visible area of the destination window in the
frame buffer. When the arrangement of windows on the
PC screen changes, modifications to the occlusion bit
map is performed by PNX1300 or host resident software.
It is important to note that there is no preset limit on the
number and sizes of windows that can be handled by the
ICP. The only limit is the available bandwidth. Thus, the
ICP can handle a few large windows or many small win-
dows. The ICP can sustain a transfer rate of 50 megapix-
els per second, which is more than enough to saturate
PCI when transferring images to video frame buffers.
2.5.6
The variable-length decoder (VLD) relieves the DSPCPU
of decoding Huffman-encoded video data streams. It can
be used to help decode high bitrate MPEG-1 and MPEG-
2 video streams. The lower bitrate of videoconferencing
can be adequately handled by DSPCPU software with-
out coprocessor.
The VLD is a memory-to-memory coprocessor. The
DSPCPU hands the VLD a pointer to a Huffman-encod-
ed bit stream, and the VLD produces a tokenized bit
stream that is very convenient for the PNX1300 image
decompression software to use. The format of the output
token stream is optimized for the MPEG-2 decompres-
sion software so that communication between the
DSPCPU and VLD is minimized.
PRELIMINARY SPECIFICATION
In SDRAM
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1
1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
U
V
Image 2
Variable-Length Decoder (VLD)
Y
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1
U
V
Image 1
Y
Overview
2-5