SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 127

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

Philips Semiconductors
7.16.2
The VO_CTL register sets the operating mode, enables
interrupts, clears interrupt flags, and initiates EVO oper-
ations. Its fields are unchanged from the TM-1000, as
shown in
cise functionality implemented by a field may be changed
Table 7-7. VO_CTL register fields
RESET
SLEEPLESS
CLOCK_SELECT Clock select.
PLL_S
PLL_T
CLKOUT
SYNC_MASTER
VO_IO1_POS
VO_IO2_POS
OL_EN
MODE
BFR1_ACK
BFR2_ACK
HBE_ACK
URUN_ACK
Field
VO Control Register (VO_CTL)
Figure 7-29
Software reset of the EVO.
The recommended software reset procedure is as follows.
• Write the desired VO_CTL state with the RESET bit set to ‘1’.
• Write the desired VO_CTL state word, this time with the RESET bit cleared to ‘0’. Both writes should have
• Finally, enable the newly selected mode by setting VO_ENABLE. This step should be done last, as a separate
After a software reset, 5 VO_CLK clock cycles are required to stabilize the internal circuitry (before enabling EVO).
Note: A hardware reset clears the CLKOUT and SYNC_MASTER bits and puts VO_CLK, VO_IO1, and VO_IO2 in
the input state. This results in a VO_CTL value of 0x32400000. In contrast, a software reset does not change
device registers. So a software reset results in a state as specified by the VO_CTL word value written during the
above-described procedure.
Disable power management.
If SLEEPLESS = 1, power-down of the EVO is prevented during global PNX1300 power-down.
00 — Select PLL VCO output as the VO_CLK source.
01 — Select PLL feedback loop divider output as VO_CLK source.
10 — Select PLL input divider output as VO_CLK source.
11 — Select DDS output directly as VO_CLK source, bypassing the PLL altogether. (Hardware reset default.)
PLL input divider division ratio.
A value of k selects division by k+1. The hardware reset default = 1, causing division by 2.
PLL feedback loop divider division ratio.
A value of k selects division by k+1. The hardware reset default = 1, causing division by 2.
Clock output.
• When CLKOUT = 1, the EVO clock generator is enabled, and VO_CLK is an output.
• When CLKOUT = 0, VO_CLK is an input, and EVO clock is provided by the external device. (Hardware reset
Sync master.
• When set, VO_IO1 and VO_IO2 are outputs. In video-refresh modes, the EVO generates horizontal and frame
• When zero, VO_IO2 is an input. (Hardware reset default.) In video-refresh modes, VO_IO2 serves as the frame
Polarity of VO_IOx_POS.
VO_IO1_POS currently has no function.
VO_IO2_POS determines the input polarity of VO_IO2.
• When ‘0’, the corresponding input triggers on the negative (high-to-low) transition of the input signal.
• When ‘1’, the input triggers on the positive (low-to-high) transition.
Overlay Enable.
Enables the YUV overlay function in video-refresh modes.
Major operating mode.
Defines the video output major operating mode, as listed in
Buffer 1 and Buffer 2 acknowledge.
When active in data-transfer modes, writing a ‘1’ to BFR1_ACK clears BFR1_EMPTY and enables Buffer 1 for
transfer until BFR1_EMPTY is set. Writing a ‘0’ to BFR1_ACK has no effect. BRF2_ACK operates similarly for
Buffer 2. Writing a ‘1’ to VO_ENABLE in data-streaming mode is the same as writing a ‘1’ to both BFR1_ACK and
BFR2_ACK, and enables both buffers 1 and 2 for transfer. Writing a ‘1’ to VO_ENABLE in message-passing mode
is the same as writing a ‘1’ to BFR1_ACK, and enables Buffer 1 for transfer. BFR2_ACK is not used in message-
passing mode, since only Buffer 1 is used.
Acknowledge HBE or URUN.
Writing a ‘1’ to these bits clears the HBE or URUN flags and resets their corresponding interrupt conditions.
VO_ENABLE set to 0.
transaction.
default.)
timing signals on VO_IO1 and VO_IO2 respectively. In message-passing mode and data-streaming mode, this
bit should always be set so that VO_IO1 and VO_IO2 generate START and END message signals respectively.
time reference. The active edge is selected by VO_IO2_POS.
and
Table
7-7, however the pre-
if PNX1300 functionality is enabled by software. Its hard-
ware
CLOCK_SELECT = 3, PLL_S = 1 and PLL_T = 1, and
all other bits to ‘0’. To ensure compatibility with future de-
vices, any undefined MMIO bits should be ignored when
read, and written as ‘0’s.
PRELIMINARY SPECIFICATION
Description
reset
Table 7-5 on page
value
is
7-13.
0x32400000
Enhanced Video Out
which
7-17
sets