SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 289

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

Philips Semiconductors
22.3
The data transfer formats for the PCI-XIO bus are shown
in
to or from the PCI-XIO Bus. The read address is the 24-
Table 22-1. PCI-XIO Bus signal definitions
22.4.1
The PCI-XIO Bus can accommodate a variety of different
devices and bus protocols. The following are examples
of devices interfaced to the PCI-XIO Bus.
Figure 22-5. PCI-XIO Bus data formats
PNX1300 PCI Signal
PCI_INTB#
PCI_AD[23:0]
PCI_AD[31:24]
PCI_PAR
PCI_C/BE0#
PCI_C/BE1#
PCI_C/BE2#
PCI_C/BE3#
PCI_CLK
PCI_FRAME#
PCI_DEVSEL#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_IDSEL#
PCI_REQ#
PCI_GNT#
PCI_PERR#
PCI_SERR
PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
Figure
DATA FORMATS
22-5. The 8-bit data field is the data transferred
Read: XIO Bus to PCI
Write: PCI to XIO Bus
PCI-XIO Bus Interface Design
Pins
24
1
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
31
31
I
I
I
Data
Data
PCI-XIO Bus Enable = XIO Bus Active As Target Device
PCI Address/Data
Even Parity for AD & C/BE
Command/Byte Enables
On XIO read, BE[3:0] = 0110b’4
On XIO write, BE[3:0] = 0111b’4
33 MHz PCI Clock: can optionally be generated by PNX1300 on board osc
PCI Address/Command Strobe + Transfer In Progress
Device Select Valid
Initiator Ready = Transfer In Progress
Target Ready
Target Requests Stop of Transaction
Chip Select for PCI Config Writes
PNX1300 Requesting PCI Bus
PNX1300 Is Granted PCI Bus
Parity Error to PNX1300
System Error from PNX1300
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
24 23
24 23
PCI Function
Read Address
Unused
bit address on the PCI-XIO Bus address lines when the
read transfer takes place.
22.4
PRELIMINARY SPECIFICATION
INTERFACE
0
0
Address bus: 16 MB
Data bus: 8 bits
IORD# = Read Enable
IOWR# = Write Enable
DS# = Data Strobe
unused
Asserted by PNX1300 = XIO Active
Asserted by PNX1300 = XIO Transfer Timing
XIO Bus Active = Global Chip Select
PCI-XIO External I/O Bus
XIO Function
22-5