SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 446
SAA7115HLBE
Manufacturer Part Number
SAA7115HLBE
Description
Video ICs ADV DGTL VIDEO DECODR
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7115HLBE.pdf
(548 pages)
Specifications of SAA7115HLBE
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 70 C
Package / Case
SOT-407
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Channels
2
Resolution
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
SAA7115HL/V1,557 SAF7115HLBE
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Philips Semiconductors
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SYNTAX
[ IF rguard ] prefr rsrc1 rsrc2
FUNCTION
DESCRIPTION
((rsrc1+rscr2) & cache_block_mask) and stores the data into the data cache. This operation is not guaranteed to be
executed. The prefetch unit will not execute this operation when the data to be prefetched is already in the data cache.
A prefr operation will not be executed when the cache is already occupied with 2 cache misses, when the operation is
issued.
execution of the prefetch operation. If the LSB of rguard is 1, prefetch operation is executed; otherwise, it is not
executed..
EXAMPLES
NOTE: This operation may only be supported in TM-1000, TM-1100, TM-1300 and
PNX1300/01/02/11. It is not guaranteed to be available in future generations of Trimedia
products.
r10 = 0xabcd, r12 = 0xd
cache_block_size = 0x40
r10 = 0xabcd, r11 = 0, r12=0xd,
cache_block_size = 0x40
r10 = 0xabff, r11 = 1, r12 =0x1,
cache_block_size = 0x40
The prefr operation loads the one full cache block size of memory value from the address computed by
The
i f rguard then {
}
cache_block_mask = ~(cache_block_size - 1)
data_cache <- mem[(rsrc1 + rscr2) & cache_block_mask]
prefr
Initial Values
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
prefr r10 r12
IF r11 prefr r10 r12
IF r11 prefr r10 r12
Operation
PRELIMINARY SPECIFICATION
Loads a cache line for the address space from
0xabc0 to 0x0xac3f from the main memory. If the
data is already in the cache, the operation is not exe-
cuted.
since guard is false, prefr operation is not executed
Loads a cache line for the address space from
0xac00 to 0x0xac3f from the main memory. If the
data is already in the cache, the operation is not exe-
cuted.
PNX1300/01/02/11 DSPCPU Operations
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
pref16x pref32x prefd
allocd allocr allocx
Result
ATTRIBUTES
SEE ALSO
dmemspec
prefr
210
No
2
5
-
-
A-148
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