SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 450

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

Philips Semiconductors
Unsigned quad 8-bit multiply most significant
SYNTAX
FUNCTION
DESCRIPTION
8-bit bytes of rsrc1 and rsrc2. All bytes are considered unsigned. The most-significant 8 bits of each 16-bit product is
written to the corresponding byte in rdest.
the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
r30 = 0x0210800e, r40 = 0xffffff02
r10 = 0, r60 = 0x80ff1010, r70 = 0x80ff100f
r20 = 1, r60 = 0x80ff1010, r70 = 0x80ff100f
As shown below, the
The
Four full-precision
[ IF rguard ] quadumulmsb rsrc1 rsrc2 → rdest
if rguard then {
}
rsrc1
16-bit products
temp ← (zero_ext8to32(rsrc1<7:0>) × zero_ext8to32(rsrc2<7:0>))
rdest<7:0> ← temp<15:8>
temp ← (zero_ext8to32(rsrc1<15:8>) × zero_ext8to32(rsrc2<15:8>))
rdest<15:8> ← temp<15:8>
temp ← (zero_ext8to32(rsrc1<23:16>) × zero_ext8to32(rsrc2<23:16>))
rdest<23:16> ← temp<15:8>
temp ← (zero_ext8to32(rsrc1<31:24>) × zero_ext8to32(rsrc2<31:24>))
rdest<31:24> ← temp<15:8>
quadumulmsb
31
unsigned
15
Initial Values
unsigned
23
unsigned
7
quadumulmsb
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls
15
0
unsigned
rdest
15
31
unsigned
operation computes four separate products of the four pairs of corresponding
7
quadumulmsb r30 r40 → r50
IF r10 quadumulmsb r60 r70 → r80
IF r20 quadumulmsb r60 r70 → r90
unsigned
unsigned
7
23
unsigned
0
0
Operation
15
15
PRELIMINARY SPECIFICATION
unsigned
rsrc2
31
unsigned
unsigned
PNX1300/01/02/11 DSPCPU Operations
×
7
7
unsigned
23
unsigned
0
×
0
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
quadumulmsb
quadavg dspuquadaddui
15
r50 ← 0x010f7f00
no change, since guard is false
r90 ← 0x40fe0100
15
unsigned
ATTRIBUTES
×
SEE ALSO
unsigned
ifir8ii
7
Result
7
unsigned
×
dspmul
0
2, 3
No
89
—
0
2
3
A-152