SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 292

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

PNX1300/01/02/11 Data Book
A table of PCI-XIO Bus Clock frequencies versus Clock
field values is shown in
PCI_CLK operating frequency should be set to observe
the frequency limits given in the AC/DC timing character-
ization data for PNX1300. Odd values of ‘Clock Frequen-
cy’ are recommended, resulting in an even divider, which
generates a 50% duty cycle PCI_CLK.
22.5.2
The XIO Bus controller has an automatic wait state gen-
erator to allow for read and write cycle times of devices
on the XIO bus.
Table 22-4. Wait state generator codes
22-8
Figure 22-10. PCI-XIO Bus timing: single byte read, 0 wait states
PCI_AD[31:24]: DATA
PCI_AD[23:0]: ADDR
PCI_C/BE1#/IOWR#
PCI_C/BE0#/IORD#
Read Sample Point
PCI_C/BE2#/DS#
PCI_INTB#/CE#
PCI_DEVSEL#
Code
PCI_FRAME#
...
PCI_TRDY#
Wait State Generator
0
1
2
7
PCI_IRDY#
PCI_CLK
PRELIMINARY SPECIFICATION
Table
Frame Time
Wait States
22-3. Note that the
PCI Command
PCI Address
PCI Address
PCI Command
PCI Command
...
0
1
2
7
Bus Turnaround
& Address Setup
22.6
The timing for the PCI-XIO bus is shown below: Note that
the ‘fat’ lines indicate active drive by PNX1300. Thin lines
indicate areas where the PNX1300 is not actively driving.
(In these areas, pull-up resistors retain the signal high for
control signals, PCI_AD lines are left floating.)
Figure 22-10
transfer.
read transfer with wait states.
timing for a DMA burst read transfer of 2 bytes, and
Figure 22-16
transfer of 2 bytes. The DMA burst transfers are shown
at maximum rate, with zero wait states. DMA burst trans-
fers with wait states insert wait states between the trans-
fers. In the read case, the IORD# enable and DS# are ex-
tended by the wait states. In the write case, the IOWR#
enable and DS# are delayed by the wait states.
XIO Addrs
XIO Transfer
PCI-XIO BUS TIMING
Figure 22-11
Read Data
shows the timing for a single byte read
shows the timing for a DMA burst write
shows the timing for a single byte
Bus Idle
Philips Semiconductors
Figure 22-14
shows the