SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 213
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SAA7115HLBE
Manufacturer Part Number
SAA7115HLBE
Description
Video ICs ADV DGTL VIDEO DECODR
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7115HLBE.pdf
(548 pages)
Specifications of SAA7115HLBE
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 70 C
Package / Case
SOT-407
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Channels
2
Resolution
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
SAA7115HL/V1,557 SAF7115HLBE
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Philips Semiconductors
Scaling and filtering of the two dimensional image re-
quires two passes of the image data through the filter,
one for vertical and one for horizontal. Scaling an image
and sending it to the PCI bus requires three transfers of
the image over the SDRAM bus: one transfer to read the
image for vertical filtering, one transfer to write the fil-
tered data back, and one transfer to read the image for
horizontal filtering and output to the PCI bus. This means
an average of SDRAM bus bandwidth of 3 x 50 = 150
MB/sec for the 1024 x 768 image case described above,
assuming a scaling factor of 1.0. A larger or smaller scal-
ing factor means that either the input or output image will
be smaller than 1024 x 768. The bandwidths required are
determined by the larger of the two images, input or out-
put. This is because all input pixels must be scanned to
generate all the output pixels.
14.2.3
Image sizes in the PNX1300 have a nominal range of 16
x 16 to 1024 x 768. Sizes smaller than 16 x 16 are pos-
sible, but are too small to be recognizable images. Imag-
es larger than 1024 x 768 (up to 64 K x 64 K) are possible
but they cannot be processed in real time and require
larger SDRAM sizes. Scaling factors have a nominal
range of 1/4 (down scaling by 4) to 4 (upscaling by 4).
Larger up and down scaling factors are possible, up to
1000 and beyond; however, very large upscaling factors
result in a large magnification of a few pixels, and very
large down scaling factors give only a few pixels as a re-
sult.
14.3
The ICP unit has no PNX1300 external pins. It interfaces
internally to the Data Highway and the PCI Interface.
14.4
The ICP unit accepts input and overlay image data to
generate output image data. The ICP accommodates a
variety of formats for the input, overlay and output data.
These image data formats define the relationship be-
tween the Y, U, and V or R, G, and B components of the
image as they are stored in memory. The ICP accepts in-
put image data in planar format, where the Y, U and V
components are in separate tables in SDRAM. The vari-
ous input image data formats differ in the position of the
U and V components relative to the Y component and the
amount of U and V data relative to the Y data.
In all modes except the YUV to RGB conversion modes,
each ICP operation processes one Y, U, or V image com-
ponent. Three separate commands are required to pro-
cess all three components of an image. Since each com-
ponent is scaled and filtered separately, the software
defines the image format and format conversion by how
it scales each component.
INTERFACE
DATA FORMATS
Image Size and Scaling
For pixel format conversion for PCI or SDRAM output
mode, each output pixel is a combination of RGB or YUV
components as defined by the output format. The YUV
input data and the RGB or YUV overlay data are com-
bined by the ICP hardware pixel by pixel to form the RGB
or YUV output pixels. Because all three YUV compo-
nents are simultaneously woven together to create each
output pixel, the ICP hardware must know the image
data format in SDRAM, defined as how the components
of the image data are to be found and combined.
In the YUV to RGB conversion mode, the ICP accepts
the following input data formats: YUV 4:2:2 co-sited,
YUV 4:2:2 interspersed, and YUV 4:2:0. In this mode, the
ICP will also accept image overlay data when PCI output
is specified. The ICP accepts image overlay data in sev-
eral combined formats: RGB 24+α, RGB 15+α, and YUV
4:2:2+α. In this mode, the ICP generates output data in
several RGB and YUV formats. These formats are com-
patible with a wide variety of PCI frame buffers.
14.4.1
The ICP image input formats define the relative positions
of the Y component and the U and V components of the
input image pixel data. There are three input formats to
the ICP: 4:2:2 co-sited, 4:2:2 interspersed, and 4:2:0 in-
terspersed. The 4:2:2 formats have 2 U and 2 V pixels for
every 4 Y pixels, so the ratio of Y to U or V is 2:1. The
4:2:0 format has 1 U and 1 V pixel for every 4 Y pixels,
so the ratio of Y to U or V is 4:1. The input formats are
given below. The input formats have a significant impact
on the 2 dimensional scaling operation.
14.4.1.1
In the YUV 4:2:2 co-sited format, the U and V pixels co-
incide with the Y pixel on every other pixel, as shown in
Figure
14.4.1.2
In the YUV 4:2:2 interspersed format, the U and V pixels
lie between the Y pixels on every other pixel of the hori-
zontal line, as shown in
14.4.1.3
In the YUV 4:2:0 interspersed format, the U and V pixels
lie between the Y pixels on every other pixel of the hori-
zontal line, as shown in
14.4.1.4
In the YUV 4:1:1 co-sited format, the U and V pixels co-
incide with the Y pixel on every fourth pixel, as shown in
Figure
PRELIMINARY SPECIFICATION
14-3.
14-6.
Image Input Formats
YUV 4:2:2 Co-Sited
YUV 4:2:2 Interspersed
YUV 4:2:0 XY Interspersed
YUV 4:1:1 Co-Sited
Figure
Figure
14-4.
14-5.
Image Coprocessor
14-3
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