SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 529

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

cache line size
carry
CCCOUNT
CCIR 656
CCIR 656 frame timing
CCIR 656 line timing
CCIR 656 pixel timing
CCIR656 serial D1
A B C
miss processing order 5-4,
miss transfer order
MMIO registers summary
noncachable region
non-cacheable region
number of sets
operation ordering
overview
overview,memory system
parameters
partial word transfers
partial words
performance evaluation support
performance events
ports
rdstatus result format
rdtag result format
replacement policies 5-3,
replacement policy
scheduling constraint
set
size
special data cache operations
special opcodes
special operation ordering
status operations 5-6,
summary of characteristics
tag field of address
tag operations 5-6,
valid bits
word in set
write misses
PCI interface register
definition
line timing
pixel timing
video connector on Enhanced Video Out
description
description table
picture
picture
A-18
5-3
table
description
description
5-3
5-3
7-5
7-5
D
5-3
5-1
Unit,picture
3-3
5-13
5-3
7-6
5-3
5-4
5-3
E
7-2
5-3
7-4
7-4
5-4
7-6
5-7
5-6
F G
5-3
5-9
5-7
5-3
5-3
5-4
5-6
5-4
11-7
5-5
5-7
7-2
5-4
5-13
5-1
5-7
5-9
5-2
H
5-6
5-12
I
J
K
L M N O P Q R S T U V W X Y Z
chroma
Chroma keying
chroma keying 14-1,
circuit board design
class code
Clipping
codec
coherency
coherency,instruction cache
command ID
compatibility
concurrency
concurrency,hidden
CONFIG_ADR
CONFIG_CTL
CONFIG_DATA
configuration header
configuration operations
control word
conversion
copyback
co-sited sampling
counter
CPU stall
curcycles
cycles
D
D1 serial
data address fields
data breakpoint
data cache
PRELIMINARY SPECIFICATION
keying
guidelines
PCI interface register
PCI interface register
software
PCI interface
PCI interface MMIO register
picture
PCI interface MMIO register
picture
PCI interface MMIO register
PCI interface
ICP vertical filter
of ICP
interspersed to co-sited
to RGB
to YUV composite
YUV to RGB 14-3,
coherency
dcb operation
8-1
A-20
3-12
7-14
7-2
5-8
A-19
5-4
5-4
14-23
14-1
11-10
11-10
14-1
3-4
7-14
12-7
5-11
3-13
6-4
11-3
11-2
5-6
5-3
5-7
14-9
11-3
14-25
14-1
14-9
11-6
11-3
5-9
7-11
11-12
11-13
11-13
Index-3