SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 286

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

PNX1300/01/02/11 Data Book
PCI transfer and is incremented for each PCI word trans-
ferred.
The XIO Bus does not generate parity during XIO Bus
write transfers or check parity during XIO Bus read trans-
fers. This allows the XIO Bus to interface to standard 8-
bit devices without having to add parity-generation and
check logic. While the XIO Bus is active, the XIO Bus log-
ic inhibits parity checking and drives the PCI Parity and
Parity Error pins so that they do not float.
Word transfer is used to transfer the bytes to and from
the PCI bus for hardware simplicity. The primary intend-
ed use of the PCI-XIO Bus is for slow devices, ROMs,
flash EPROMs and I/O. Because the PCI-XIO bus is so
22-2
Figure 22-1. Partial PNX1300 chip block diagram
Digital
Camera
DMSD
or Raw
Video
Digital
Audio
Serial
JTAG
Clock
XIO Bus
Controls
PRELIMINARY SPECIFICATION
Video In
Audio In
Audio Out
2.5 GOPS
Glueless
Flash
EPROM I/F
DSPCPU
400 MIPS
PCI - XIO Bus AD[31:0]
PCI and External I/O (PCI-XIO) Bus Interface
D$
I$
SDRAM
Highway
SDRAM: 32-bit data
XIO
I/O Device
MMI
much slower than the PNX1300, there is time available
for the PNX1300 to pack and unpack the words. In the
case of ROMs and flash EPROMs, the data is typically
compressed, requiring the PNX1300 CPU to both un-
pack and decompress the data.
The PCI-XIO Bus Controller logic reconfigures the byte
enables as control signals for the attached XIO Bus chips
during XIO Bus transfers. It also drives the PCI_TRDY#
signal to the PCI Bus for each transfer. The PCI Bus byte
enables are reconfigured to generate XIO Bus timing sig-
nals: Read (IORD), Write (IOWR) and Data Strobe (DS).
These signals allow ROM, flash EPROM, 68K and x86
devices to be gluelessly interfaced to the XIO Bus. For a
single device, the PCI_INTB# line is used as the global
Synchronous
Serial I/F
I
Co Processor
2
Video Out
VLD Assist
C Interface
PNX1300
PCI
I/O Device
Image
Philips Semiconductors
PCI Bus
Controls
V.34 Modem
Video Out
I
CCIR 601
Digital
2
C Bus