SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 45

Video ICs ADV DGTL VIDEO DECODR

SAA7115HLBE

Manufacturer Part Number
SAA7115HLBE
Description
Video ICs ADV DGTL VIDEO DECODR
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SAA7115HLBE

Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 70 C
Package / Case
SOT-407
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Channels
2
Resolution
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
SAA7115HL/V1,557 SAF7115HLBE
Philips Semiconductors
1.9.7.10
Notes: 1. For best high speed SDRAM operation, 50-ohm matched PCB traces are recommended for all MM_xxx signals.
1.9.7.11
The following specifications meet the PCI Specifications, Rev. 2.1 for 33-MHz bus operation.
Notes: 1. See the timing measurement conditions in
f
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Symbol
SDRAM
on-PCI
su-PCI
su-PCI (ptp)
rst-PCI
rst-clk-PCI
rst-off-PCI
CS
PD
OH
SU
IH
val-PCI (Bus)
val-PCI (ptp)
Off-PCI
h-PCI
Symbol
1. PCI Clock skew between two PCI devices must be lower than 1.8ns instead of the 2 ns as specified in PCI
2. Equal load circuit. MM_CLK0 and MM_CLK1 are matched output buffers.
3. The center of the two rising edges on MM_CLK0, MM_CLK1 are used as the clock reference point.
4. MM_CLK0 is used as a reference clock.
2. Minimum times are measured at the package pin with the load circuit shown in
3. REG# and GNT# are point-to-point signals and have different input setup times. All other signals are bused.
4. See the timing measurement conditions in
5. RST# is asserted and de-asserted asynchronously with respect to CLK.
6. All output drivers are floated when RST# is active.
7. For the purpose of Active/Float timing measurements, the Hi-Z or ‘off’ state is defined to be when the total current delivered
2.1 specification
MM_CLK frequency
Skew between MM_CLK0, CLK1
Propagation delay of data, address, control
Output hold time of data, address and control
Input data setup time
Input data hold time
Use 27-33 ohm series terminator resistors close to PNX1300/01/02/11 in the MM_CLK0 and MM_CLK1 line only.
Propagation delay guarantee is defined from 50% point of clock edge to 50% level on D/A/C.
Output hold time guarantee is defined from 50% point of clock edge to 50% level on D/A/C.
Input setup time requirement is defined as data value 50% complete to 50% level on clock.
Input hold time requirement is defined as minimum time from 50% level on clock to 50% change on data.
with the load circuit shown in
through the component pin is less than or equal to the leakage current specification.
SDRAM interface timing for PNX1300/01/02/11 speed grades.
PCI Bus timing
Clk to signal valid delay, bused signals
Clk to signal valid delay, point-to-point signals
Float to active delay
Active to float delay
Input setup time to CLK - bused signals
Input setup time to CLK - point-to-point signals
Input hold time from CLK
Reset active time after power stable
Reset active time after CLK stable
Reset active to output float delay
Parameter
Figure 1-6
Parameter
and
Figure
Figure
Figure
Min
PNX1300
1.5
2.0
0
1-4.
1-5.
143
1-7.
Max
0.05
143
4.7
PRELIMINARY SPECIFICATION
Min
PNX1301
1.5
1.5
0
166
Max
0.05
Min.
0.2
166
100
4.2
12
2
2
2
7
1
1
Min
1.5
PNX1301
1.5
0
180
Max
Figure
11
12
28
40
0.05
Max Min Max Min Max Units
166
4.2
1-8. Maximum times are measured
PNX1311
1.5
1.5
0
166
Units
ms
ns
ns
ns
ns
ns
ns
ns
µs
ns
0.05
166
4.2
PNX1302
1.5
1.5
0
Notes
1,2,3
5,6,7
1,2,3
200
1,7
3,4
3,4
1
4
5
5
0.05
183
3.7
Pin List
MHz
ns
ns
ns
ns
ns
1-19
N
o
e
s
1
2
3
3
4
4
t

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