SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 488
SAA7115HLBE
Manufacturer Part Number
SAA7115HLBE
Description
Video ICs ADV DGTL VIDEO DECODR
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7115HLBE.pdf
(548 pages)
Specifications of SAA7115HLBE
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 70 C
Package / Case
SOT-407
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Channels
2
Resolution
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
SAA7115HL/V1,557 SAF7115HLBE
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Philips Semiconductors
Unsigned 16-bit load with index
SYNTAX
FUNCTION
DESCRIPTION
to 32 bits, and writes the result in rdest. If the memory address computed by rsrc1 + rsrc2 is not a multiple of 2, the
result of
endian depending on the current setting of the bytesex bit in the PCSW.
defined only for 32-bit loads and stores.
modification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written and
the data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is not
changed and
EXAMPLES
r10 = 0xd00, r20 = 2, [0xd02] = 0x22,
[0xd03] = 0x11
r50 = 0, r40 = 0xd04, r30 = 0xfffffffc,
[0xd00] = 0x84, [0xd01] = 0x33
r60 = 1, r40 = 0xd04, r30 = 0xfffffffc,
[0xd00] = 0x84, [0xd01] = 0x33
r70 = 0xd01, r30 = 0xfffffffc
The
The result of an access by
The
[ IF rguard ] uld16r rsrc1 rsrc2 → rdest
if rguard then {
}
if PCSW.bytesex = LITTLE_ENDIAN then
else
temp<7:0> ← mem[rsrc1 + rsrc2 + (1 ⊕ bs)]
temp<15:8> ← mem[rsrc1 + rsrc2 + (0 ⊕ bs)]
rdest ← zero_ext16to32(temp<15:0>)
uld16r
uld16r
bs ← 1
bs ← 0
uld16r
Initial Values
uld16r
operation loads the 16-bit memory value from the address computed by rsrc1 + rsrc2, zero extends it
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
is undefined but no exception will be raised. This load operation is performed as little-endian or big-
has no side effects whatever.
uld16r
uld16r r10 r20 → r80
IF r50 uld16r r40 r30 → r90
IF r60 uld16r r40 r30 → r100
uld16r r70 r30 → r110
to the MMIO address aperture is undefined; access to the MMIO aperture is
Operation
PRELIMINARY SPECIFICATION
PNX1300/01/02/11 DSPCPU Operations
r80 ← 0x00002211
no change, since guard is false
r100 ← 0x00008433
r110 undefined (0xd01 +(–4) is not a multiple
of 2)
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
uld16 ild16 uld16d ild16d
ild16r uld16x ild16x
ATTRIBUTES
SEE ALSO
Result
uld16r
dmem
198
4, 5
No
—
2
3
A-190
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