IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 72
IPS-VIDEO
Manufacturer Part Number
IPS-VIDEO
Description
MegaCore Suite W/ 17 DSP Video/image Processing Functions
Manufacturer
Altera
Type
-r
Specifications of IPS-VIDEO
Software Application
IP CORE, SUITES
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
Suite of IP Functions for Video and Image Processing
License
Initial License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
- Current page: 72 of 214
- Download datasheet (6Mb)
4–10
Video and Image Processing Suite User Guide
Ancillary Data Packets
Figure
packets, and how they are split into symbols.
Figure 4–8. Three Symbols in Parallel
Figure 4–9. Two Symbols in Parallel
Figure 4–10. One Symbol in Parallel
Ancillary data packets send ancillary packets between MegaCore functions. Ancillary
data packets are typically placed between a control data packet and a video data
packet and contain information that describes the video data packet, for example
active format description codes.
An ancillary data packet can contain one or more ancillary packets, each ancillary
packet starts with the code 0, 3FF, 3FF.
4–8,
Control data packet type identifier
(4 bits in least significant symbol,
Figure
Control data packet type identifier
(4 bits in least significant symbol,
X’s for unused symbols)
Control data packet type identifier
(4 bits in least significant symbol,
Control data, reference numbers to Table 4-5
Start
X’s for unused symbols)
Control data, reference numbers to Table 4-5
Start
X’s for unused symbols)
4–9, and
Start
15
X
15
X
X
2
1
15
Figure 4–10 on page 4–10
Control data, reference numbers to Table 4-5
3
2
1
4
3
1
6
5
4
6
5
2
9
8
7
8
7
3
X
9
4
End
Symbols in most significant bits
Symbols in middle significant bits
Symbols in least significant bits
5
End
Symbols in most significant bits
Symbols in least significant bits
6
show examples of control data
7
8
May 2011 Altera Corporation
9
Avalon-ST Video Protocol
End
Chapter 4: Interfaces
Related parts for IPS-VIDEO
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet: