IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 196

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

7–4
Clocked Video Input
Table 7–4. Clocked Video Input Control Register Map (Part 1 of 2)
Video and Image Processing Suite User Guide
0
1
2
3
4
5
6
Address
Control
Status
Interrupt
Used Words
Active Sample Count
F0 Active Line Count
F1 Active Line Count
Register
Table 7–4
The width of each register is 16 bits.
describes the Clocked Video Input MegaCore function control register map.
Bit 0 of this register is the Go bit:
■
Bits 3, 2, and 1 of the Control register are the interrupt enables:
■
■
■
Bit 0 of this register is the Status bit:
■
Bits 2 and 1 of the Status register are not used.
Bits 6, 5, 4, and 3 are the resolution valid bits:
■
■
■
■
Bit 7 is the interlaced bit:
■
Bit 8 is the stable bit:
■
Bit 9 is the overflow sticky bit:
■
Bit 10 is the resolution bit:
■
Bits 2 and 1 are the interrupt status bits:
■
■
■
The used words level of the input FIFO.
The detected sample count of the video streams excluding blanking.
The detected line count of the video streams F0 field excluding blanking.
The detected line count of the video streams F1 field excluding blanking.
Setting this bit to 1 causes the Clocked Video Input MegaCore function to
start data output on the next video frame boundary. Refer to
on page 5–12
Setting bit 1 to 1, enables the status update interrupt.
Setting bit 2 to 1, enables the stable video interrupt.
Setting bit 3 to 1, enables the synchronization outputs (sof, sof_locked,
refclk_div).
Data is being output by the Clocked Video Input MegaCore function when this
bit is asserted. Refer to
When bit 3 is asserted, the SampleCount register is valid.
When bit 4 is asserted, the F0LineCount register is valid.
When bit 5 is asserted, the SampleCount register is valid.
When bit 6 is asserted, the F1LineCount register is valid.
When asserted, the input video stream is interlaced.
When asserted, the input video stream has had a consistent line length for
two of the last three lines.
When asserted, the input FIFO has overflowed. The overflow sticky bit stays
asserted until a write of is performed to this bit.
When asserted, indicates a valid resolution in the sample and line count
registers.
When bit 1 is asserted, the status update interrupt has triggered.
When bit 2 is asserted, the stable video interrupt has triggered.
The interrupts stay asserted until a write of 1 is performed to these bits.
for full details.
“Control Port” on page 5–12
Description
Chapter 7: Control Register Maps
May 2011 Altera Corporation
for full details.
“Control Port”
Clocked Video Input