IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 197

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 7: Control Register Maps
Clocked Video Output
Table 7–4. Clocked Video Input Control Register Map (Part 2 of 2)
Clocked Video Output
Table 7–5. Clocked Video Output Control Register Map (Part 1 of 3)
May 2011 Altera Corporation
7
8
9
10
11
12
13
0
1
Address
Address
Total Sample Count
F0 Total Line Count
F1 Total Line Count
Standard
SOF Sample
SOF Line
Refclk Divider
Control
Status
Register
Register
Table 7–5
map. The width of each register is 16 bits.
describes the Clocked Video Output MegaCore function control register
The detected sample count of the video streams including blanking.
The detected line count of the video streams F0 field including blanking.
The detected line count of the video streams F1 field including blanking.
The contents of the vid_std signal.
Start of frame sample register. The sample and sub-sample upon which the SOF
occurs (and the sof signal triggers):
■
■
Start of frame line register. The line upon which the SOF occurs measured from
the rising edge of the F0 vertical sync.
Number of cycles of vid_clk (refclk) before refclk_div signal triggers.
Bit 0 of this register is the Go bit:
■
Bits 3, 2, and 1 of the Control register are the interrupt enables:
■
■
■
■
Bit 0 of this register is the Status bit:
■
Bit 1 of the Status register is unused.
Bit 2 is the underflow sticky bit:
■
Bit 3 is the frame locked bit.
■
Bits 0–1 are the subsample value.
Bits 2–15 are the sample value.
Setting this bit to 1 causes the Clocked Video Output MegaCore function to
start video data output. Refer to
Setting bit 1 to 1, enables the status update interrupt.
Setting bit 2 to 1, enables the locked interrupt.
Setting bit 3 to 1, enables the synchronization outputs (vid_sof,
vid_sof_locked, vcoclk_div).
When bit 3 is set to 1, setting bit 4 to 1, enables frame locking. The Clock
Video Output attempts to align its vid_sof signal to the sof signal from the
Clocked Video Input MegaCore function.
Data is being output by the Clocked Video Output MegaCore function when
this bit is asserted. Refer to
When bit 2 is asserted, the output FIFO has underflowed. The underflow
sticky bit stays asserted until a 1 is written to this bit.
When bit 3 is asserted, the Clocked Video Output has aligned its start of
frame to the incoming sof signal.
“Control Port” on page 5–21
Description
Description
“Control Port” on page 5–21
Video and Image Processing Suite User Guide
for full details.
for full details.
7–5